Wrap-Around-Contact

A wrap-around contact is a conductive connection that reaches additional surfaces of a transistor’s source/drain region, commonly its top and sidewalls. The geometry aims to increase useful contact area and improve current access within a small footprint. It is a source/drain connection; the separate gate controls conduction in the channel. Its benefit depends on interface quality, contact coverage, semiconductor current spreading and the resistance-capacitance tradeoffs of the completed device.

Identify what the metal surrounds. In a conventional nanosheet implementation, the contact connects local wiring to source/drain semiconductor. A gate-all-around electrode instead surrounds the channel through a gate dielectric. These are different electrical functions at different locations. The main illustration is a cross-section through a source/drain block, with the gate outside the cut. IBM’s VLSI 2017 nanosheet work evaluates wrap-around contacting for reduced extrinsic resistance, while imec also discusses increased contact area in tightly scaled structures.

Geometric area is only part of contact resistance. Under a simple uniform-interface approximation, R_contact ≈ ρ_contact / A, where ρ_contact is specific contact resistivity and A is contacted area. Adding sidewall area can help, but real current distribution is nonuniform. Current crowding, source/drain spreading resistance, interface properties and the metal path all influence the measured result. Specific contact resistivity, contact resistance and width-normalized resistance are different quantities. Comparing shapes requires consistent extraction methods and matched semiconductor, doping, interface and operating conditions.

Coverage needs an explicit cross-section. A top-and-sidewall contact does not automatically reach the underside of the source/drain. Patent US10559656B2 describes a wrap-all-around architecture that additionally contacts below the source/drain epitaxy, including an underlying cavity in the proposed flow. That is a specific documented embodiment, rather than proof that all devices called wrap-around contacts use the same geometry or fabrication sequence. The appropriate description states which semiconductor faces are contacted and which neighboring regions remain electrically isolated.

Integration must create a continuous, suitable interface. Surface preparation, interfacial reaction or liner formation, conformal coverage and metal fill work together. Depending on the process, an interfacial silicide or another conductive layer may contribute to the connection. Imec’s 2017 IITC paper specifically studies an ALD-Ti contact approach for scaled FinFET devices. This is evidence for one investigated integration route, not a universal contact-metal prescription. The completed structure must provide continuity on the intended faces without bridging to the gate or an adjacent device.

The circuit sees both resistance and capacitance. Reduced contact or source/drain access resistance can improve delivered drive current, while additional metal near the gate can change parasitic coupling. A 2026 ESSERC modeling study explicitly examines full wrap-around contacts as a way to improve source/drain resistance with a capacitance penalty in its assessed structures. Its projected behavior should retain that modeling context. A useful comparison includes the complete access path, gate coupling, load, bias and thermal assumptions before translating contact geometry into a speed or energy claim.

Verification separates the interface from the rest of the path. Cross-sectional inspection checks contacted faces, liner continuity, voids, isolation and semiconductor damage. Dedicated electrical structures help extract contact and access contributions, while device measurements test leakage, drive current and variability. Circuit evaluation then determines whether the resistance reduction outweighs associated capacitance and integration costs. Reliability and current-density limits also need assessment. A larger visible metal envelope alone cannot establish lower specific contact resistivity, successful gate isolation or a manufacturing-ready process.

Sources and further reading. [IBM VLSI 2017: nanosheets and wrap-around contact evaluation](https://research.ibm.com/publications/stacked-nanosheet-gate-all-around-transistor-to-enable-scaling-beyond-finfet); [Imec IITC 2017: ALD-Ti wrap-around contact study](https://imec-publications.be/entities/publication/92270656-6570-4163-a6d0-cbec48244107); [Imec on increased contact area in scaled GAA structures](https://www.imec-int.com/en/articles/imec-demonstrates-for-the-first-time-functional-ring-oscillators-based-on-stacked-gate-all-around-silicon-nanowire-transistors); [US10559656B2: a documented wrap-all-around contact embodiment](https://patents.google.com/patent/US10559656B2/en); [ESSERC 2026: contact and source/drain resistance-capacitance modeling](https://epapers2.org/esserc2026/ESR/paper_details.php?paper_id=8261).

Read wrap-around contact as an access-geometry choice: identify the contacted surfaces, characterize the interface and current spreading, then verify the resulting resistance, capacitance and circuit behavior together.