3D NAND Backside Source Contact Etch

Backside source contact is a third way into the same source-line plate that CSL contact fill and side-wall ONO removal already reach — and it exists only because bonded architectures create a brand-new backside surface that a CMOS-under-array design never has.

Backside revealed
array wafer's substrate removed
Backside source-contact mask
targets source-line plate depth
Backside source contact etch
shallower than TSC, stops at the plate
Contact fill
barrier + W plug
Third source route complete
alongside CSL and side-wall ONO removal

It is shallower and simpler than its neighbor, through-silicon contact, because its target is much closer to that new surface.

Backside Source Contact — Reaching the Source Plate From Behind a third route to the same source-line plate, used only once the array wafer has been flipped and thinned Periphery CMOS wafer (bonded, flipped underneath) array stack — word lines, slit, CSL already built from the original top original substrate removed by backside Si thinning/reveal backside source contact stops at the source-line plate, not the periphery wafer TSC, for comparison — goes all the way to the periphery wafer source-line plate — this contact's target, mid-stack from this new direction A third route to a plate that already has two CSL contact fill already reaches the source-line plate vertically from the array's original top, and side-wall ONO removal reaches it laterally through the channel — backside source contact adds a third path, from the new backside surface, useful specifically because that surface now exists at all. shallower than TSC — it only needs to reach the plate, not all the way through to the periphery wafer beneath it

This contact is not routing to the periphery wafer — it is routing to the array's own source plate, from a direction that only became available after thinning. Where through-silicon contact etches all the way down to the bonded periphery wafer underneath, backside source contact only needs to reach the source-line plate sitting partway through the array stack, a much shorter and less demanding etch by comparison.

The source-line plate already has two routes into it before this one is added. CSL contact fill reaches it vertically, straight down through the slit from the array's original top; side-wall ONO removal reaches it laterally, through the channel itself. Backside source contact adds a third, reaching the same plate from the new backside surface that thinning exposed — not because the plate was unreachable before, but because this direction simply wasn't available until the wafer was flipped and ground down.

Why bother with a third route to a plate that already has two? Backside routing in a bonded design often needs its own direct connection to the source without threading back through the array's front-side wiring, so this contact gives backside metal layers a shorter, more direct path to the source plate than routing all the way back through the slit-based CSL connection would require.

A barrier and tungsten plug finish this contact the same way they finish TSC and most other vias in the flow, after which backside metal can connect to the source plate directly, independent of whatever routing happens on the array's original front side.

Backside source contact is a small, specific consequence of choosing a bonded architecture at all: YMTC's Xtacking and other CBA-style designs gain a whole new surface to etch and route from once thinning is complete, and this contact is one of the more modest things that new surface makes possible — a shorter path to a plate the front side already reaches two different ways.

Take 3d nand backside source contact etch further

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