3D NAND Channel Hole Etch
Channel hole etch is the step that actually makes 3D NAND possible, and it is the single hardest etch in the entire flow: a hole cut at an aspect ratio of 50 to 80-to-1 or more, straight down through 200 to 300-plus alternating layers the film-stack step deposited, right after the staircase has carved landings into the same stack from the side.
No single etch pass can hold that profile for the full depth, which is why the hole is cut in two separate passes that have to line up perfectly.
The lower-deck etch goes first, and it is where bowing, twisting, and CD loading do the most damage. At 50 to 80-to-1 aspect ratio, a channel hole etched in a single continuous pass drifts off a straight vertical line (bowing), rotates slightly as it deepens (twisting), or narrows unevenly from top to bottom (CD loading) — any one of which can leave a hole that never reaches full depth, a defect called "not-open." Many fabs now run this step cryogenically, cooling the wafer during etch specifically to suppress that drift.
The inter-deck plug, or joint etch, is the seam between the two passes. A sacrificial fill bridges the lower deck once it is etched, giving the wafer a flat, stable surface to pattern the upper-deck mask on top of — and that upper-deck mask has to align to the lower-deck hole closely enough that the finished channel reads as one continuous hole rather than two misaligned ones.
The upper deck repeats the same etch challenge at a shallower effective depth, after a sacrificial-poly recess clears the inter-deck fill back out of the hole, continuing the same channel down to meet the lower deck exactly where the plug etch left it.
A bottom punch finishes the job the channel hole etch exists to set up: it opens the ONO film at the very bottom of the hole so the channel will later contact the source-line plate underneath — sometimes preceded by a selective epitaxial growth recess (SEG recess) on vendors that grow epi silicon at the channel base — and a channel-poly recess, core-oxide ("macaroni") recess, and drain-poly etch-back finish shaping the plug at the top of the hole.
Every vendor runs this same lower-deck/plug/upper-deck/punch sequence — Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking — because the physics of a 50 to 80-to-1 aspect-ratio hole through 200 to 300-plus layers does not change with the name on the stack; what differs between them is how many decks the hole is split into and how high the layer count climbs before a third deck becomes unavoidable.