3D NAND Peripheral Deep Contact Etch

Peripheral deep contact, or Peri CT (sometimes Peri MC), reaches peripheral logic the same way TAC reaches the periphery underneath the array — a single deep via through a lot of accumulated height — except it does so from a region that was never part of the array footprint in the first place.

Peripheral logic finished
outside the array footprint
Thick oxide fill deposited
to match array-side stack height
Peri CT mask
lands outside the array entirely
Peri CT deep etch
through oxide fill, no array layers
Barrier + W fill
contact plug
Back-end routing
connects peripheral logic to the rest of the die

That distinction changes what makes the etch hard: TAC has to avoid structures on the way down; Peri CT simply doesn't encounter any.

Peripheral Deep Contact (Peri CT) — Outside the Array, Not Under It a deep via landing on logic beside the memory array, through a region with no ONON stack at all array region — full ONON stack, channel holes, slit periphery region — ordinary logic, no ONON stack here peripheral logic circuit Peri CT etch deep, through thick oxide fill no array layers in the way TAC, for comparison — same depth, but cuts through a dummy region inside the array footprint Depth without density, not depth through density TAC reaches the periphery from inside the array footprint, through a dummy oxide region deliberately kept free of memory structures. Peri CT doesn't need that trade-off at all — it lands outside the array entirely, so the depth comes from a thick dielectric fill, not from threading past channel holes and word lines. sometimes called Peri MC — contact to the peripheral logic's own metal, same job regardless of the label

The peripheral region beside the array has no ONON stack, no channel holes, and no slit — it is ordinary logic, built the way peripheral CMOS always is. Because the array and its periphery are usually fabricated at roughly the same overall height, a thick dielectric fill sits over the peripheral logic to bring its surface level up to match the array's top, and Peri CT has to etch straight down through that fill to land on the logic underneath.

TAC and Peri CT solve similar-sounding problems from genuinely different starting conditions. TAC exists because the periphery sits directly under the array in a CMOS-under-array design, so it has to cut through a dummy oxide region carved out of the array on purpose, sacrificing array real estate to make the path possible at all. Peri CT never has that trade-off, because its landing point was never inside the array footprint — the depth comes entirely from oxide fill, not from threading past memory structures.

That difference shows up directly in what the etch has to avoid. TAC's dummy region exists specifically because the alternative is etching through live word lines, channel holes, or the slit; Peri CT's path is clear by construction, since there is nothing from the array side anywhere near it to avoid in the first place.

The fill thickness is really the main variable this etch has to handle. Because the oxide fill over peripheral logic is deposited to roughly match the array's stack height, Peri CT's required depth tracks the array's own layer count indirectly — a 200-layer array and a 300-layer array call for different fill thicknesses over the periphery, and Peri CT's depth target moves with that difference even though it never touches the array stack itself.

Peri CT is the plainer etch of the two deep-reach contacts in this flow: Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking all still need to connect their peripheral logic to the rest of the die through a layer of fill that has grown taller as layer counts have climbed, and Peri CT is simply the contact that makes that connection without ever having to care about what the array side of the die is doing.

Take 3d nand peripheral deep contact etch further

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