3D NAND Peripheral Sti Etch

Peripheral STI etch is the very first etch in the entire 3D NAND flow, and it looks nothing like any of the array-side etches that follow it — because it runs before the array exists at all, on bare silicon, using the same shallow-trench isolation process any ordinary logic chip would use.

Bare silicon wafer
nothing deposited yet
STI hard-mask pattern
defines active-area boundaries
STI trench etch
shallow, into bare substrate
Oxide gap-fill + CMP
isolates neighboring transistors
HV/LV gate module next
periphery transistors built here

Everything that makes 3D NAND's array etches distinctive — aspect ratio, layer count, multi-depth contacts — simply isn't present yet at this stage.

Peripheral STI Etch — the Very First Etch in the Entire Flow ordinary logic isolation, run before a single array layer is deposited Silicon substrate (wafer) HV transistor LV transistor HV transistor STI trench STI trench oxide fill isolates neighbors oxide fill isolates neighbors Peri STI gate etch, HV GOX array film stack ...and beyond The only etch in this entire flow with no 3D structure involved channel holes, staircases, and slits all cut through a stack that doesn't exist yet when peri STI runs — this etch happens first, on flat silicon, exactly the way it would on any ordinary logic chip.

This etch separates one peripheral transistor from its neighbor, the same way STI does on any chip. A shallow trench is cut into the bare silicon substrate between what will become adjacent transistor active areas, then filled with oxide, so current in one transistor's active region has no path to leak into the one sitting right beside it.

Peripheral logic needs more than one kind of isolation, because it needs more than one kind of transistor. High-voltage transistors, used for the charge pumps and word-line drivers that need to switch tens of volts, sit next to low-voltage transistors doing ordinary logic switching — and STI is what keeps those very different operating voltages from interfering with each other across the same silicon.

An STI recess sometimes follows the trench fill, pulling the oxide back slightly to set the exact topology the gate module needs — a small adjustment, but one that has to happen before gate oxide growth and gate etch can proceed on a predictable surface.

This is the one etch in the whole flow untouched by anything array-related. Channel hole, staircase, and slit etch all have to contend with a 200-to-300-plus layer stack that doesn't exist yet when peri STI runs — this step happens on flat, bare silicon, using a process any fab running ordinary CMOS logic would recognize immediately, with no 3D NAND-specific complexity at all.

Peri STI etch is proof that even the most exotic 3D memory chip starts with the most ordinary possible step: before Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, or YMTC's Xtacking cut a single channel hole, every one of them first isolates its peripheral transistors with the same shallow-trench process logic fabs have used for decades.

Take 3d nand peripheral sti etch further

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