Bicmos Logic 1980s Deploy Bicmos in Bus Drivers and Backplane Loads

# BiCMOS Logic (Late 1980s): Step 13 — Deploy BiCMOS in Bus Drivers and Backplane Loads

## 1. Bus Lines Are the Other Obvious Heavy-Load Case

An on-chip bus line, or a signal routed to an off-chip pad and onward to a backplane, accumulates capacitance from every device tapped along its length plus the wiring capacitance of the trace itself, frequently reaching into the hundreds of picofarads for a long backplane trace — well above the crossover capacitance from Step 10, and often well above the load range where even a widened CMOS driver (Step 1) remains competitive. These are exactly the nodes bus-driver and output-pad designers in this era targeted with BiCMOS output stages.

## 2. The System-Level Case for Paying the Cost Here

Unlike a sense amplifier, a bus or backplane driver's performance affects not just one chip's internal timing but an entire board or system's signaling budget, so the propagation-delay and drive-current advantages quantified in Steps 8 and 9 translate directly into system-level speed headroom — a faster bus driver lets the rest of the system run at a higher clock rate, or tolerate a longer physical bus, for the same timing budget. This system-level leverage is part of why early ASIC libraries, covered next in Step 15, specifically offered BiCMOS output-pad cells as an optional, premium cell type rather than a default.

## 3. Companion Diagram One: Quantitative View

Bus-Line Delay: the Load Range Where BiCMOS Dominates t_pd against bus/backplane load capacitance, extended range CMOS driver, even widened per Step 1 BiCMOS bus driver crossover from Step 10, now far to the left of this range input-capacitance penalty paid upstream, still slow here holds delay down across the whole heavy range backplane loads routinely exceed hundreds of picofarads this is the load regime BiCMOS output pads were specifically built for

## 4. Companion Diagram Two: Structural View

From Die to Backplane: Where the Capacitance Accumulates capacitance sources along a signal's path off-chip ON-CHIP BUS every tapped device adds capacitance along the line OUTPUT PAD BiCMOS driver placed here, at the boundary BACKPLANE TRACE largest single contributor, off-chip wiring the pad driver sees the sum of everything downstream of it

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