Bicmos Logic 1980s Deploy Bicmos in SRAM Sense Amplifiers

# BiCMOS Logic (Late 1980s): Step 12 — Deploy BiCMOS in SRAM Sense Amplifiers

## 1. Why a Sense Amplifier Is a Natural BiCMOS Node

A static RAM's sense amplifier reads the small voltage difference between a bit line and its complement and has to resolve that difference into a full logic-level output as fast as possible, because sense-amp delay sits directly on the memory's critical read path. The bit lines themselves present substantial capacitance — the accumulated junction and wiring capacitance of every memory cell attached along the line — which places sense amplifiers squarely above the crossover point established in Step 10, making them one of the clearest cases where a bipolar output stage earns back its fixed overhead.

## 2. What BiCMOS Sense Amplifiers Delivered in Practice

Production SRAMs built on BiCMOS processes in this era used bipolar differential pairs or bipolar output stages specifically within the sense-amplifier block, while leaving the memory array's own storage cells and most of the surrounding control logic as pure CMOS to preserve density and static power across the much larger area the array itself occupies. The result was SRAMs with access times meaningfully faster than an equivalent pure-CMOS design at the same cell density, because the one circuit block on the critical timing path — the sense amplifier — was the one block upgraded to bipolar.

## 3. Companion Diagram One: Quantitative View

Access Time: Pure CMOS vs BiCMOS Sense Amp, Same Array SRAM access time, identical cell array, two sense-amp implementations pure CMOS sense amplifier BiCMOS sense amplifier, same array the access-time gain this swap alone delivers limited by bit-line capacitance and CMOS output drive bipolar output resolves the bit-line swing faster only the sense amp changes — the array stays pure CMOS either way the critical-path block is exactly where the crossover analysis says to spend bipolar

## 4. Companion Diagram Two: Structural View

One Bipolar Block Inside an Otherwise-CMOS SRAM floorplan allocation within a representative BiCMOS SRAM CMOS MEMORY ARRAY bulk of the die, density and low power preserved BIT LINES heavily loaded, the capacitance that crosses the line BIPOLAR SENSE AMP small area, placed exactly on the critical path selective placement again — bipolar only where the load and timing demand it

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