Bicmos Logic 1980s Build Bicmos Standard Cell Libraries for Early Asics

# BiCMOS Logic (Late 1980s): Step 15 — Build BiCMOS Standard-Cell Libraries for Early ASICs

## 1. What an ASIC Library Has to Offer a Designer

Early application-specific IC design flows worked from a standard-cell library — a fixed catalog of pre-characterized logic gates, each with known delay, power, and area, that a designer places and wires automatically rather than hand-laying-out transistors. A BiCMOS-capable fab offered its ASIC customers a library that included the usual pure-CMOS cells for bulk logic alongside a smaller set of BiCMOS output-buffer and driver cells, explicitly positioned for use at the specific heavy-load, high-fan-out, or critical-path nodes Steps 12 through 14 identified.

## 2. Why the Library Kept the Two Cell Types Separate Rather Than Merging Them

Because Step 11 showed BiCMOS losing at light load, a sound library never offered a BiCMOS version of every gate as a drop-in replacement; it offered BiCMOS variants only for the output-stage and buffer cell types where the heavy-load case was common, and left ordinary combinational gates — AND, OR, NAND, NOR, flip-flops — as pure CMOS only. Placement-and-routing tools of this era needed explicit guidance, usually from the designer rather than from automated optimization, about which specific nets justified the BiCMOS cell's area and power premium, since the tools of the time could not reliably run Step 10's crossover analysis automatically across an entire netlist.

## 3. Companion Diagram One: Quantitative View

Library Composition: Few BiCMOS Cells, Many CMOS Cells cell-type counts in a representative BiCMOS ASIC library pure CMOS cells — the vast majority of the catalog BiCMOS cells — buffers and output drivers only the intended usage ratio, by design every combinational and sequential primitive a small, deliberately narrow set the library mirrors the crossover rule from Step 10, not an even split most of a design's area still comes entirely from the CMOS side of the catalog

## 4. Companion Diagram Two: Structural View

Where a Designer Was Expected to Reach for the BiCMOS Cell library guidance for cell selection, by net type ORDINARY LOGIC NET pure CMOS cell, default choice, no exception DESIGNER JUDGMENT manual flag required on heavy-load or critical nets OUTPUT / BUFFER NET BiCMOS cell, used deliberately and sparingly automated tools of this era could not make this call unassisted

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