Cfet Logic Route Independent Source Drain Contacts to Both Stacked Devices

# CFET (Complementary FET): Step 10 — Route Independent Source/Drain Contacts to Both Stacked Devices

## 1. A Genuinely Hard Interconnect Problem

Every transistor needs its source and drain terminals wired to the rest of the circuit, not just its gate. In a side-by-side nanosheet layout, the bottom device's source/drain contacts and the top device's source/drain contacts — meaning the two different transistors' terminals — are both sitting at the same height, directly accessible from above by ordinary vertical contact vias. In a CFET stack, the bottom device's source/drain regions are now buried underneath the top device's entire structure, and a contact reaching down to them from above has to pass by or through the top device's own source/drain regions and gate without touching them.

## 2. Why This Is Harder Than It Sounds

A contact via that needs to reach the bottom device cannot simply be drilled straight down through the top device's footprint, because doing so would short the via to whatever top-device material it passes through along the way. The practical answer explored in the research literature is to route the bottom device's contact around the top device's footprint laterally, landing on an exposed region of the bottom device's source/drain that extends past the top device's own edge, then bringing that contact back up to the regular interconnect stack from the side rather than straight through the top. This adds real area and real process complexity relative to a layout where every contact simply drops straight down.

## 3. Top and Bottom Devices May Need Different Contact Strategies Entirely

Because the top device's source/drain is reachable directly from above without obstruction, while the bottom device's source/drain is not, a CFET standard cell plausibly needs two distinct contact schemes within the same cell — a conventional top-down contact for the top device, and a side-access or staggered contact for the bottom device — rather than one uniform contact process applied symmetrically to both devices the way nanosheet GAA's source/drain epitaxy and contact scheme (`gaa_nanosheet_2020s` Step 8) could be.

## 4. Why This Problem Sits at the Center of CFET's Overall Difficulty

Among the integration challenges this series has described — thermal budget (Step 4), bonding yield (Step 5), middle dielectric quality (Step 7), and the gate-sharing choice (Steps 8-9) — independent source/drain contact routing is frequently cited in the research literature as the single hardest unsolved interconnect problem standing between CFET as a research demonstration and CFET as a manufacturable standard-cell library, because it has no straightforward analog anywhere in the nanosheet or finfet process flows this series' predecessors already solved.