copper damascene

Copper damascene is the dominant interconnect fabrication method using copper metal fill in damascene-patterned dielectric trenches and vias. **Why copper**: Cu resistivity (1.7 uOhm-cm) is ~40% lower than Al (2.7 uOhm-cm). Better electromigration resistance. Enables faster, more reliable interconnects. **Cu challenge**: Cannot be dry-etched by conventional RIE. Must use damascene (inlaid) approach. Diffuses rapidly in Si and SiO2, requiring barriers. **Process sequence**: Etch dielectric features, PVD TaN/Ta barrier, PVD Cu seed, electroplate Cu fill, Cu CMP (multi-step), post-CMP clean, cap layer deposition. **Electroplating**: Bottom-up fill using electrochemical deposition with accelerator/suppressor/leveler additives. Superfill provides void-free filling of high-AR features. **Barrier**: TaN provides diffusion barrier, Ta provides Cu adhesion and promotes (111) texture for electromigration resistance. **CMP**: Multi-step - bulk Cu removal, barrier removal, buff. Slurry chemistry with BTA inhibitor controls dishing. **Cap layer**: SiCN or SiN capping layer over Cu prevents oxidation and Cu diffusion into next dielectric level. Also serves as etch stop. **Electromigration**: Cu has higher EM resistance than Al. Bamboo grain structure and proper interfaces extend EM lifetime. **Adoption**: First production use by IBM at 220nm node (1997). Now universal for interconnect.