copper electroplating

**Copper Electroplating** is the **electrochemical deposition process that fills trenches and vias with copper for chip interconnects** — the primary metallization method for BEOL wiring at every technology node since IBM's 130nm copper revolution in 1997. **Process Flow** 1. **Barrier Deposition**: PVD TaN/Ta liner prevents Cu diffusion into dielectric (2–5 nm). 2. **Seed Layer**: PVD Cu thin film (~30–80 nm) provides the conductive surface for electroplating. 3. **Electroplating (ECD)**: Wafer submerged in CuSO4 + H2SO4 electrolyte. Cu2+ ions reduce at cathode (wafer) to fill features. 4. **Anneal**: 200–400°C grain growth anneal — large grains reduce resistivity. 5. **CMP**: Remove excess Cu (overburden) — planarize back to dielectric surface. **Electroplating Chemistry** The electrolyte contains critical organic additives: - **Accelerator** (SPS/MPS): Adsorbs at bottom of features, increases local deposition rate → enables bottom-up fill. - **Suppressor** (PEG + Cl-): Adsorbs at top of features, suppresses deposition rate → prevents premature closure. - **Leveler** (JGB, Diallylamine): Smooths the final surface by preferentially depositing in recesses. **Bottom-Up Fill Mechanism (Superfill)** - Accelerator concentrates at feature bottom as sidewalls approach each other. - This creates a "curvature-enhanced" deposition that fills from bottom up — void-free. - Without proper additive balance: voids (incomplete fill) or seams (weak boundaries) form. **Challenges at Advanced Nodes** - **Seed coverage**: Narrow trenches (< 20 nm) make continuous PVD seed coverage difficult. - Solution: ALD Cu seed, or Co/Ru liner that catalyzes seedless plating. - **Void formation**: High aspect ratio vias (> 5:1) prone to pinch-off. - **Grain boundaries**: Nanoscale grains increase resistivity — anneal optimization critical. - **Alternative metals**: At metal pitches below 20 nm, Cu resistivity increases sharply due to electron scattering from grain boundaries and liners. Co, Ru, and Mo being evaluated for lowest metal levels. Copper electroplating is **the workhorse metallization technique of modern semiconductor BEOL** — a chemistry-driven process where additive engineering determines whether chip interconnects are defect-free or yield-killing.