electrolytic copper plating damascene

**Copper Electrochemical Deposition (ECD)** enables **bottom-up superfilling of fine-feature damascene vias/trenches via accelerator/suppressor/leveler additive system, replacing tungsten plugs with lower-resistance copper**. **Damascene Process Overview:** - Conventional: etch via/trench in dielectric, fill with metal, CMP planarize - Copper damascene: use ECD instead of CVD or PVD tungsten - Advantage: copper resistivity 2x lower than tungsten (8 µΩ·cm vs 15 µΩ·cm) - Cost: copper electroplating cheaper than tungsten CVD **Bottom-Up Superfilling (Superconformal Deposition):** - Problem: conventional ECD deposits thicker at feature top (current density gradient) - Solution: accelerator/suppressor additives modify deposition rate spatially - Accelerator: SPS (bis(3-sulfonatopropyl) disulfide) promotes deposition - Suppressor: PEG (polyethylene glycol) inhibits deposition on flat surfaces - Leveler: small-molecule additive (coumarin, cationic dyes) suppresses protrusions - Net result: bottom-up filling without overburden **Copper Seed Layer:** - Purpose: provide initial conductivity for ECD (copper is deposited, not sputtered) - Composition: Ta or TaN barrier (5-10 nm) + Cu seed (50-200 nm) - Deposition: PVD sputtering (conformality critical, especially high-aspect) - Thickness control: critical (too thin = incomplete coverage, too thick = adds resistance) **Copper ECD Bath Chemistry:** - Copper sulfate (CuSO₄): copper source, 1 M typical - Sulfuric acid (H₂SO₄): electrolyte, reduces solution resistance - Chloride (Cl⁻): anion, affects copper nucleation/growth - PEG (suppressor): concentration ~0-2 ppm typical - SPS (accelerator): concentration ~0.5-5 ppm - Leveler: concentration optimized (1-100 ppm depending on chemistry) **Current Distribution and Plating:** - Current density: 1-10 A/dm² typical (applied voltage ~3-6V) - Overpotential: drives deposition reaction (higher = faster, less uniform) - Field distribution: uneven current density in deep trenches (via bottom starved) - Superfilling chemistry: compensates via local enhancement at feature bottom **Void and Seam Defects:** - Void formation: trapped gas bubbles, incomplete fill - Seam: linear cavity from grain boundary pinchoff - Micro-void: sub-micron voiding in copper bulk - Cause: accelerator/suppressor imbalance, hydrogen entrapment - Mitigation: pulse plating, additives tuning, CMP thickness **Overburden and CMP Removal:** - Overburden: excess copper plating above feature (several micrometers typical) - CMP (chemical mechanical polishing): removes overburden, planarizes surface - CMP chemistry: oxidizing slurry (H₂O₂ + abrasive SiO₂), copper dishing risk - Dishing: CMP preferentially removes copper faster than dielectric (creates depression) **Bath Replenishment and Maintenance:** - Additives depletion: accelerator/suppressor consumed during plating - Maintenance: regular bath analysis (titration, chromatography) - Replenishment cycle: add additives to maintain concentration - Bath life: extended via careful maintenance (months vs. weeks) **Copper Plating for Different Features:** - Via fill: small aspect ratio, straightforward superfilling - Trench fill: larger width, more critical (current density variation) - Interconnect metal: bulk fill before CMP (secondary process step) **Environmental and Cost Considerations:** - Bath disposal: toxic copper waste requires treatment - Labor: bath maintenance requires trained operators - Cost advantage: offset by CMP (removal tool expensive) - Environmentally: aqueous process vs. gas-phase (preferable) **Advanced ECD Variations:** - Pulse electroplating: modulate current on/off for improved uniformity - Direct plating: eliminate seed layer (nascent process) - Selective plating: mask technique for area-specific deposition Copper ECD remains backbone of interconnect fill in advanced CMOS nodes—continuous additive system improvements enabling superfilling of narrower, deeper features as technology scales.