die yield

Die yield is the **percentage of dies on a processed wafer that pass all electrical tests** and are functional. It's the single most important metric for semiconductor manufacturing economics. **Yield Formula** Die Yield = Good Dies / Total Dies × 100% Using the **Poisson model**: Y = e^(-D₀ × A), where D₀ = defect density (defects/cm²) and A = die area (cm²). For a more realistic clustered-defect model: **Murphy's** or **negative binomial** models are used. **Typical Die Yields** • **Mature process, small die**: **95-99%** (high-volume, well-optimized process) • **Mature process, large die**: **85-95%** (larger area catches more defects) • **New process ramp, small die**: **70-85%** (process still being optimized) • **New process ramp, large die**: **30-60%** (combination of immature process + large area) • **First silicon (initial lots)**: **5-20%** (expected—process needs extensive tuning) **Why Yield Decreases with Die Size** A random defect anywhere on the die kills it. Larger dies present a **bigger target** for defects. If defect density is 0.1/cm² and die area is 1 cm², yield ≈ 90%. At 4 cm² die area, yield drops to ≈ 67%. At 8 cm² (massive GPU), yield ≈ 45%. **Yield Improvement (Yield Learning)** **Defect reduction**: Identify and eliminate particle sources, process excursions, and equipment issues. **Design fixes**: Metal fill optimization, redundant vias, design-for-manufacturability (DFM) rules. **Process optimization**: Tighter SPC control, APC feedback, recipe tuning. **Yield ramp**: Typical trajectory—months of intense yield learning to progress from first silicon to HVM yield targets. **Yield Impact on Cost** Yield improvement is the most powerful lever for reducing semiconductor cost. Improving yield from 50% to 90% nearly **halves** the cost per good die without any change in wafer cost or die design.