Bitline Stack Etch
The bitline stack etch — BL Etch or GBL Etch — cuts straight down through a tall sandwich of materials in one continuous pass: a SiN cap on top, then tungsten, then a TiN or WSi barrier, then polysilicon at the bottom contacting the bitline contact beneath it, and holding a clean, vertical sidewall through all four materials at once is what makes this etch genuinely difficult rather than routine. Every material in that stack etches differently under the same plasma conditions, so a recipe that cleanly cuts tungsten can leave the polysilicon underneath rough or undercut, and a recipe tuned for polysilicon can leave tungsten with ragged, re-sputtered edges — this etch has to satisfy all four materials' etch behavior inside one uninterrupted process.
The transition from one material to the next inside this stack is where the etch is most likely to go wrong, which is why this recipe runs as a sequence of sub-steps rather than one fixed chemistry start to finish. Moving from tungsten into the TiN or WSi barrier beneath it, and then from that barrier into polysilicon, each demands a different balance of reactive and physical etch components, so the plasma chemistry and bias conditions are typically stepped through several sub-recipes timed to each material boundary — a mismatch at any single transition can leave a notch, an undercut, or a re-sputtered residue of the material above smeared onto the sidewall of the material below, any of which weakens the finished bitline's electrical integrity or its resistance to later process steps.
This etch's results propagate directly into the bitline's resistance and signal integrity, since the stack it defines is the actual physical conductor carrying every read and write signal across the array. A bitline that comes out of this etch with a rough sidewall, a narrowed cross-section at a material transition, or inconsistent profile from line to line doesn't just look imperfect under inspection — it directly raises bitline resistance or introduces line-to-line resistance variation that shows up later as timing margin loss or sense-amplifier read errors, which is why the bitline stack etch gets qualified with the same statistical rigor as the cell-array etches earlier in this flow despite sitting in what looks, on paper, like a simpler conductor-formation step.
Periphery gate integration sometimes shares this same stack and etch sequence, which adds another layer of constraint to the recipe. On process generations where the periphery gate is built using a bitline-gate (BG) integration scheme, the same high-k/metal-gate-compatible stack and etch has to satisfy both the array's bitline requirements and the periphery transistor's gate requirements at once, run on high-aspect-ratio multi-material etch platforms from Lam Research and Tokyo Electron tuned specifically for this kind of layered conductor stack rather than a single homogeneous material.
Read the bitline stack etch through a *one-cut-four-materials* lens rather than a *tall-line-etch* lens — the real difficulty was never the height of the stack, it was making four materials with four different etch personalities come out of one continuous process with a single, unbroken, electrically sound sidewall.