TSV Etch

The TSV etch is the first step in this entire project that cuts through single-crystal bulk silicon substrate itself rather than any deposited film, and that single difference forces a completely different etch technology: the Bosch process, which alternates passivation and etch cycles rather than running one continuous chemistry, producing a distinctive scalloped sidewall ripple that no other etch covered so far in this project leaves behind. A through-silicon via has to punch tens to hundreds of micrometers deep through the wafer's own bulk material to create a vertical electrical path between a DRAM die and whatever it needs to stack with — typically another DRAM die in an HBM stack — and ordinary continuous-chemistry plasma etching simply can't sustain the combination of depth, sidewall verticality, and etch rate this requires without the Bosch process's cyclic approach.

When this etch happens relative to the rest of the front-end and back-end flow is a genuine, consequential integration choice this project hasn't had to confront before, because TSVs can be formed via-first, via-middle, or via-last, and each option imposes different thermal-budget constraints on everything else in the process. A via-first TSV is etched and filled before any transistor is built, so the filled via has to survive every high-temperature front-end step that follows, including transistor anneals that would damage copper if it were already present — which usually pushes via-first designs toward tungsten fill instead; a via-middle TSV forms after transistors exist but before most of the back-end metal, splitting the thermal-budget problem between front-end and back-end constraints; a via-last TSV, etched from the backside after the wafer has already been thinned and all front-end and back-end processing is complete, avoids the thermal-budget problem entirely because no further high-temperature steps remain, which is why via-last with copper fill has become the dominant approach for HBM-style stacking specifically.

Depth and diameter here are both far larger than anything else in this project, but the resulting aspect ratio is still demanding enough to inherit the same geometric discipline that governed the storage-node hole etch at the opposite end of the size scale. A TSV might run 5 to 10 micrometers in diameter and 50 to 100 micrometers deep, dimensions that look enormous next to a storage-node hole's nanometer-scale diameter, but the resulting aspect ratio — often 10:1 or higher — still demands the same bowing, twisting, and sidewall-taper control that extreme aspect ratio etches require at any size, which is a reminder that aspect ratio, not absolute dimension, is what actually determines how hard an etch is to control.

Read through a cut-through-the-substrate-itself lens, the TSV etch is where this project's entire etch sequence steps outside the deposited-film world that every prior front-end and back-end round operated inside — this is the one etch cutting through the same bulk crystalline silicon the whole device was built on top of, and it needs a fundamentally different cyclic chemistry specifically because that material, that depth, and that aspect ratio combination has no other practical way through.