DRAM Scaling 1974 Compare Two Geometries Same Electrical Terms

# Step 5 — Compare the Two Geometries on the Same Electrical Terms: Why the Industry Forked

## 1. Equalizing the Electrical Baseline: The 35 fF Target

When trench and stacked capacitors are evaluated on identical electrical terms—delivering the same 35 fF storage capacitance within the same lateral cell footprint—their physical trade-offs resolve into an irreducible choice between etching depth and surface topography. In Robert Dennard’s 1968 1T1C baseline, the signal voltage swing $\Delta V$ detected by the sense amplifier is determined by the capacitance ratio:

$$\Delta V = \frac{C_s}{C_s + C_{bl}}\,V_{dd}$$

To maintain a reliable sensing margin ($\Delta V \ge 150\text{--}200\ \text{mV}$) against bit-line capacitance $C_{bl}$ and sense-amp noise, $C_s$ must remain above $30\text{--}35\ \text{fF}$, regardless of cell architecture. Assuming an Oxide-Nitride-Oxide (ONO) dielectric with an equivalent oxide thickness $t_{\text{ox,eq}} = 7\ \text{nm}$ ($C_{\text{diel}} \approx 5.0\ \text{fF}/\mu\text{m}^2$), both geometries must provide an identical physical surface area:

$$A_{\text{req}} = \frac{C_s}{C_{\text{diel}}} = \frac{35\ \text{fF}}{5.0\ \text{fF}/\mu\text{m}^2} = 7.0\ \mu\text{m}^2$$

In a sub-micron cell with opening diameter $d = 0.5\ \mu\text{m}$, the two architectures generate this $7.0\ \mu\text{m}^2$ through completely different geometric mechanisms:
* The Trench Capacitor: Only the single outer sidewall perimeter ($P = \pi d \approx 1.57\ \mu\text{m}$) is available. It must etch to depth $d_{\text{etch}} = 7.0 / 1.57 \approx 4.5\ \mu\text{m}$, forcing a steep aspect ratio $\text{AR} \approx 9:1$.
* The Stacked Crown Capacitor: Both inner and outer sidewalls are coated ($P \approx 2\pi d \approx 3.14\ \mu\text{m}$). With Hemispherical Grained Silicon (HSG) adding a $1.8\times$ texturing gain ($P_{\text{eff}} \approx 5.65\ \mu\text{m}$), the required height is only $h_{\text{stack}} = 7.0 / 5.65 \approx 1.25\ \mu\text{m}$ ($\text{AR} \approx 2.5:1$).

Quantitative Comparison: Delivering 35 fF at 0.5 µm Pitch side-by-side dimensional accounting: etch depth vs. topographic stack height TRENCH CAPACITOR (ETCH DOWN) Perimeter P: π · d = 1.57 µm (Single outer wall) Required Dimension: Depth detch = 4.5 µm into substrate Aspect Ratio (AR): 9 : 1 (High RIE etch difficulty) Wafer Topography Impact: ✓ Δh = 0 µm (Perfect wafer surface planarity) ✗ Substrate punch-through risk; requires buried collar STACKED CROWN CAPACITOR (BUILD UP) Perimeter Peff: 2πd × 1.8 HSG = 5.65 µm (Dual walls + HSG) Required Dimension: Height hstack = 1.25 µm above plane Aspect Ratio (AR): 2.5 : 1 (Modest etch difficulty) Wafer Topography Impact: ✗ Δh = 1.25 µm (Severe optical defocus cliff) ✓ 100% immune to bulk leakage and alpha particles THE GOVERNING TRADE-OFF ✓ Trench trades high aspect ratio (9:1) to keep the surface flat (Δh = 0) ✓ Stacked trades low aspect ratio (2.5:1) for severe surface topography (Δh = 1.25 µm) Both architectures deliver 35 fF, but they distribute manufacturing difficulty to completely different fab modules.

## 2. Why the Semiconductor Industry Forked into Two Camps

Because neither architecture held an absolute advantage across all manufacturing steps, the global semiconductor industry split along corporate and geographical lines throughout the 1980s and 1990s.

The Industrial Fork: Two Decades of Competing DRAM Alliances how corporate process strengths divided the worldwide memory industry THE TRENCH ALLIANCE IBM · Siemens / Infineon · Texas Instruments Foundational Belief: "Surface planarity is non-negotiable for sub-micron lithography." Key Manufacturing Core: • Mastered deep reactive-ion etching of silicon • Invented oxide collar to isolate trenches in the bulk • Avoided early CMP planarization completely Ultimate Scaling Limit: • Trench-to-trench substrate punch-through below 90 nm • Aspect ratios exceeded 40:1, hitting etch stop THE STACKED ALLIANCE Hitachi · Toshiba · NEC · Samsung · Micron Foundational Belief: "Substrate isolation and soft-error immunity are paramount." Key Manufacturing Core: • Mastered thin-film poly crowns and HSG texturing • Eliminates deep substrate leakage and alpha soft errors • Pioneered Chemical Mechanical Polishing (CMP) The Decisive Historical Pivot: • When CMP matured in the 1990s, topography vanished • Stacked became the universal architecture for modern DRAM The Resolution of the Industry Split: Both architectures succeeded in volume for over a decade. But when CMP solved the topography problem, the stacked capacitor won the endgame.

## 3. Place This Step in the Project's Own Lineage

Step 5 provides the core comparative synthesis that defines the 1974 DRAM scaling era:
1. The Circuit Baseline Preserved: Both geometries strictly adhere to the 1968 Dennard 1T1C storage principle. Neither changes the bit-line charge-sharing equation. What they alter is purely how the required physical plate area ($A_{\text{req}} = 7.0\ \mu\text{m}^2$) is packed into a $0.5\ \mu\text{m}$ lateral cell pitch.
2. The Anatomy of the Historical Split: The trench camp bet on silicon reactive-ion etching to preserve flat surfaces for lithography. The stacked camp bet on polysilicon thin films and dielectric isolation to guarantee soft-error immunity. Each camp reflected the core competencies of its founders: IBM’s lithography-centric fab discipline versus the Japanese memory consortium's relentless mastery of thin-film deposition and chemical texturing.
3. Setting Up the Subsequent Process Steps: This fundamental divergence sets the agenda for the remainder of the series:
- Steps 6 and 7 will drill into the unique physics of the trench path: isolating the trench from the substrate (Step 6) and void-free filling (Step 7).
- Step 8 will tackle the Achilles' heel of the stacked path: planarizing the tall topography via Chemical Mechanical Polishing (CMP).
- Step 9 will calculate the final cost-accounting metric: capacitance recovered per unit of process complexity.

Step 5 confirms that the fork was not an ideological accident, but the logical consequence of balancing aspect ratio against topography in the third dimension.

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