DRAM Scaling 1974 Retrospective Leaving Plane Only Way Forward

# Step 10 — The 1974 Retrospective: When Leaving the Plane Became the Only Way Forward

## 1. The Immutable Circuit Law and the Collapse of Two Dimensions

Robert Dennard’s 1968 1T1C circuit equations held without compromise, but the physical silicon implementation had to leave the two-dimensional plane to survive. In 1974, Dennard and his IBM colleagues codified classical MOSFET scaling (*Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions*), proving that if device geometries ($L, W, t_{\text{ox}}$) and supply voltages ($V_{dd}$) shrink by a constant factor $\kappa$, transistor switching speed increases by $\kappa$ while power density remains flat. But in dynamic RAM, the storage node was bound by an irreducible signal-to-noise floor:

$$\Delta V = \frac{C_s}{C_s + C_{bl}}\,V_{dd} \ge 150\text{--}200\ \text{mV} \implies C_s \ge 35\ \text{fF}$$

Because bit-line parasitic capacitance $C_{bl}$ and sense-amplifier thermal offsets do not scale with lithography, the charge packet $Q_s = C_s V_{dd}$ could not be reduced. Under planar 2D scaling, the physical area available for the storage plate shrank as $A_{\text{cell}} \propto 1/\kappa^2$. By the $0.5\ \mu\text{m}$ technology node, planar capacitance collapsed to less than $3.5\ \text{fF}$—a ten-fold deficit that rendered classical planar DRAM physically impossible.

To save dynamic RAM from extinction, memory designers were forced to break the cardinal rule of planar photolithography: they left the flat silicon plane and conquered the vertical $Z$-axis.

The 1974 DRAM Scaling Retrospective: The 3D Migration from Dennard's 1968 planar baseline through the trench/stacked divide to modern 3D convergence 1968: PLANAR Dennard 1T1C Cs ∝ Area (2D) Zero Topography The Crisis: At 0.5 µm, Cs < 3.5 fF ΔV collapses to zero 2D Planar Fails TRENCH (ETCH DOWN) IBM · TI · Siemens Buried N⁺ Plate Thick Oxide Collar Core Advantage: Flat Wafer Surface Δh = 0 µm for litho Fatal Limit: Bulk punch-through < 90 nm AR > 40:1 etch stop STACKED (BUILD UP) Hitachi · Toshiba · Samsung Polysilicon Crowns HSG Micro-Texturing Core Advantage: Soft-Error Immunity Dual-sidewall area (4πrh) Resolved By CMP: Polishing flattened 1.5 µm cliff Thin films easily reworked MODERN CONVERGENCE MIM Stacked Pillar ZrO₂ / Al₂O₂ High-k TiN Metal Electrodes The Universal Standard: Samsung · SK Hynix · Micron All use stacked MIM Next Horizon: 4F² Vertical Gate 1T1C Monolithic 3D DRAM THE TRIUMPH OF THE THIRD DIMENSION ✓Dennard's Circuit Equations Preserved: Signal swing ΔV remained invariant while physical silicon expanded into 3D ✓ The Decisive Industrial Lesson: When planar geometry hits physical limits, topological expansion is the only sustainable path The 1974 DRAM scaling revolution created the playbook that later enabled 3D NAND and FinFET logic.

## 2. The Universal Architectural Template: From DRAM to NAND and FinFETs

The decision to abandon the 2D plane in DRAM was not an isolated episode; it was the historic pioneer for the entire semiconductor industry.

The Universal Pattern: Leaving the Plane Across All Semiconductors how DRAM's 1985 3D leap foreshadowed the evolution of NAND flash and advanced CMOS logic 1. DRAM CAPACITORS (1985) The 2D Planar Limit: Capacitance collapsed below 3.5 fF Signal-to-noise margin vanished The 3D Solution: Deep Trench & Stacked Crowns Z-axis provides 38 fF storage Impact on Fabs: Introduced CMP, deep RIE, and conformal high-aspect-ratio CVD 2. NAND FLASH (2013) The 2D Planar Limit: Floating gates held < 10 electrons Cell-to-cell capacitive crosstalk The 3D Solution: 3D BiCS / V-NAND Vertical Strings Drilling 200+ stacked word lines Impact on Fabs: Replaced sub-10 nm lithography with extreme aspect ratio etching 3. CMOS LOGIC (2011) The 2D Planar Limit: Short-channel subthreshold leakage Drain induced barrier lowering (DIBL) The 3D Solution: FinFET → GAA Nanosheets → CFET Gate wraps around 3D channel Impact on Fabs: Eliminates planar transistors; 3D gate electrostatic control The Enduring Legacy of 1974: DRAM proved that Moore's Law is not a flat planar law—it is an engineering mandate to exploit the third dimension whenever planar physics surrenders.

## 3. Place This Step in the Project's Own Lineage

Step 10 completes the comprehensive ten-step investigation of the 1974 DRAM Scaling Era:
1. The Trajectory Synthesized: The series opened in Step 1 with Robert Dennard’s 1974 scaling equations colliding with the immutable 1968 1T1C storage floor ($C_s \ge 35\ \text{fF}$). Step 2 established the architectural ultimatum: etch down into the silicon substrate or build up into the open space above the gate. Steps 3, 6, and 7 traced the trench path (deep RIE, buried plates, oxide collars, and void-free filling). Steps 4 and 8 traced the stacked path (polysilicon crowns, soft-error immunity, and CMP global planarization). Step 5 contrasted their fundamental geometry, and Step 9 delivered the objective cost-accounting ledger.
2. The Core Physical Insight: Moore's Law did not survive because dimensions kept shrinking passively; it survived because semiconductor architects repeatedly redesigned planar components into complex 3D structures. The DRAM capacitor was the first electronic component to break out of the plane, establishing the manufacturing disciplines (deep reactive-ion etching, chemical mechanical polishing, atomic layer deposition) that later rescued NAND flash (3D V-NAND) and microprocessor logic (FinFETs and GAA nanosheets).
3. Closing the Capstone: Step 10 permanently integrates the 1974 DRAM scaling revolution into the knowledge corpus, providing a complete, mathematically rigorous, and historically verified reference for how the memory industry conquered the third dimension.

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