What Is an Etch 3D NAND Onon Filmstack

An etch 3D NAND ONON filmstack (etch 3D NAND ONON etch filmstack) is an ultra-thick periodic dielectric superlattice composed of 128 to over 300 alternating nanolaminate pairs of silicon dioxide ($SiO_2$, typically $25\text{–}35\text{ nm}$) and silicon nitride ($Si_3N_4$, typically $20\text{–}30\text{ nm}$). In modern ultra-high-density 3D NAND flash memory (spanning 232-layer, 280-layer, and $>300$-layer architectures), total filmstack thickness reaches $6\text{ to }10\text{ }\mu\text{m}$. Patterning this multi-layer structure requires excavating billions of vertical memory hole channels and slit trenches through the entire laminate in a single or multi-tier (deck) dry etch pass. With channel aspect ratios exceeding $AR > 80:1$ (and approaching $100:1$ at sub-70nm top critical dimensions), 3D NAND ONON high-aspect-ratio reactive ion etching (HAR RIE) represents the physical pinnacle of dielectric plasma processing. The process demands cryogenic chuck temperatures ($-40^\circ\text{C}\text{ to }-70^\circ\text{C}$), multi-megawatt-per-wafer RF bias voltages ($V_{\text{pp}} > 5\text{–}10\text{ kV}$), and unsaturated fluorocarbon gases ($C_4F_6, C_4F_8, CH_2F_2, CH_3F$) mixed with oxygen and argon to combat aspect-ratio-dependent etching (ARDE / RIE lag), channel twisting, feature bowing, striation, and premature etch stop. At a high level, the architectural anatomy of a 3D NAND ONON etch filmstack and its selective HAR dry etch sequence looks like this:

Substrate CMOS foundation
CMOS under Array (CuA / COP) peripheral circuits + source plane
Periodic ONON superlattice deposition
128-300+ alternating pairs of SiO2 (28nm) / Si3N4 (24nm) via PECVD
3D NAND ONON high-aspect-ratio dry etch sequenceCryogenic wafer cooling, high-voltage RF bias, and alternating SiO2/Si3N4 volatilization
Boron-doped carbon hardmask open
Pattern transferred through 3-5μm thick a-C / SOC hardmask
Alternating lattice volatilization
C4F6 / CH2F2 / O2 / Ar continuously etches SiO2 and Si3N4 pairs
Cryogenic sidewall fluoropolymer freeze
T_wafer = -60°C freezes protective CFx polymer to stop hole bowing
High-voltage directional ion drive
10 kV pulsed RF bias drives ions straight to AR > 80:1 bottom
↻ 200+ layer deep penetration
Vertical channel profile (89.8°)
Zero channel twisting, striation, or bowing across 8μm depth
Bottom poly-Si contact landing
Sub-50nm CD landed with zero punch-through or micro-trenching

A few principles are essential for understanding how 3D NAND ONON etch filmstacks are constructed, how periodic oxide-nitride chemistry is navigated simultaneously, and why cryogenic high-voltage RIE overcomes transport starvation:

Filmstack structural hierarchy and functional layers. An advanced 3D NAND ONON memory hole etch filmstack consists of five integrated layers:
1. *Amorphous Carbon Hardmask (ACL / APF):* $3.0\text{ to }5.5\text{ }\mu\text{m}$ of boron-doped amorphous carbon ($a\text{-C}:B$) deposited by high-temperature PECVD ($>550^\circ\text{C}$). High $sp^3$ tetrahedral bonding and boron doping ($5\text{–}15\%$) maximize physical hardness and thermal stability, enabling the mask to withstand hours of intense fluorine ion bombardment without facet degradation.
2. *Dielectric Capping & Anti-Reflective Layers:* $50\text{ to }100\text{ nm}$ of silicon oxynitride ($SiON$) and low-temperature oxide ($LTO$) that planarize the hardmask and serve as the lithographic imaging foundation.
3. *Periodic ONON Superlattice Stack:* $6\text{ to }10\text{ }\mu\text{m}$ total thickness consisting of $128\text{ to }300+$ alternating bilayers:
- *Oxide Layer ($SiO_2$, $25\text{–}32\text{ nm}$):* Acts as vertical isolation between adjacent word lines.
- *Sacrificial Nitride Layer ($Si_3N_4$, $20\text{–}26\text{ nm}$):* Acts as the placeholder layer later stripped via wet hot phosphoric acid ($H_3PO_4$) and replaced with atomic-layer-deposited tungsten ($W$) metal gates (gate-replacement / "word-line replacement" process).
4. *Select Gate / Source Line Stop Matrix:* $100\text{ to }200\text{ nm}$ of heavily phosphorus-doped polysilicon ($n^+\text{-poly}$) or tungsten silicide ($WSi_x$) bottom source plane.
5. *Underlying CMOS under Array (CuA / COP):* Lower-tier peripheral logic transistors and tungsten interconnects protected beneath the array to reduce die size by $>30\%$.

3D NAND ONON Superlattice Etch Filmstack Multi-tier superlattice, cryogenic fluorocarbon kinetics, and HAR AR > 80:1 memory hole etch ONON Filmstack & Channel Hole Boron-Doped ACL (3.5-5.0μm) High-sp³ Carbon | Hardmask AR > 10:1 SiO2 (28nm) Si3N4 (24nm) 128 - 300+ ONON Bilayers Total Superlattice Depth: 6.0 - 9.0 μm Bottom Poly-Si Source Plane CMOS under Array (CuA / COP) Peripheral Logic & Row Decoders Cryogenic Fluorocarbon Kinetics & ARDE Control 1. Simultaneous Oxide-Nitride Removal (C4F6 / CH2F2 / O2): SiO2: SiO2 + 2CF2 → SiF4 ↑ + 2CO ↑ | Si3N4: Si3N4 + 12F + 4H → 3SiF4 ↑ + 4HCN ↑ Tuned C:F and C:H ratios match etch rates of SiO2 and Si3N4 to avoid lateral scallops 2. Cryogenic Passivation Freeze (T_wafer = -60°C): Low chuck temperature condenses fluoropolymer on sidewalls, suppressing bowing Enables ultra-straight 89.8° sidewalls without channel hole twisting or distortion 3. High-Voltage Pulsed RF Bias (V_pp > 8-10 kV): Overcomes ARDE / RIE lag and ion deflection at AR > 80:1 aspect ratios Drives directional ions 8μm deep; halts selectively on bottom poly-Si contact pad Stack Height: 6-9 μm | Aspect Ratio: > 80:1 | T_wafer: -60°C | RF Bias: > 8 kV Cryogenic RIE (-60°C) Freezes sidewall polymer 10 kV Pulsed RF Bias Defeats RIE lag at AR > 80:1 Boron-Doped Carbon Mask Withstands 8μm deep etch 3D NAND ONON superlattices stack 128 to 300+ alternating pairs of SiO2 and Si3N4 totaling 6 to 9 microns cryogenic wafer cooling and 10kV pulsed bias enable vertical memory hole profiles without bowing or channel distortion

High-aspect-ratio reactive ion etch physics and chemical kinetics. The extreme aspect ratio ($AR > 80:1$) and massive multi-layer depth ($>7\text{ }\mu\text{m}$) introduce severe physical failure modes that dictate modern 3D NAND ONON etch recipes:
- *Simultaneous Dual-Material Removal Kinetics:* The plasma must etch through alternating layers of silicon dioxide and silicon nitride without producing serrations or horizontal scalloping at layer boundaries. To achieve an identical vertical etch rate across both materials, hydrofluorocarbon additives ($CH_2F_2, CH_3F$) are introduced into a $C_4F_6/Ar/O_2$ base plasma. Hydrogen radicals selectively react with nitrogen in $Si_3N_4$ to desorb volatile $HCN$, accelerating the nitride removal rate to match the oxygen-assisted volatilization rate of $SiO_2$ ($SiO_2 + 2CF_2 \rightarrow SiF_4 \uparrow + 2CO \uparrow$).
- *Cryogenic Wafer Cooling to Combat Bowing:* As aspect ratios exceed $40:1$, neutral radicals accumulate near the upper neck of the memory hole, causing spontaneous isotropic chemical etching known as "bowing." In cryogenic RIE (operating between $-40^\circ\text{C}$ and $-70^\circ\text{C}$), the thermal desorption rate of fluorocarbon polymers drops exponentially. A dense, stable protective polymer skin condenses on upper channel sidewalls, completely suppressing lateral chemical attack and ensuring a vertical sidewall profile ($89.8^\circ\text{–}90.0^\circ$).
- *Mitigating ARDE and Channel Twisting with Multi-Kilovolt RF Bias:* Deep inside high-aspect-ratio holes, neutral gas transport becomes Knudsen-diffusion-limited, while electrical charge accumulation on insulating sidewalls generates parasitic electrostatic fields that deflect incoming positive ions, causing channel hole distortion and "twisting." To overcome this transport barrier and charge deflection, state-of-the-art etch reactors apply ultra-high pulsed peak-to-peak RF bias voltages ($V_{\text{pp}} > 8\text{–}10\text{ kV}$). These ultra-energetic ions punch straight down through the Knudsen starvation zone, maintaining vertical trajectories and landing cleanly on the bottom source plane with sub-50nm critical dimension precision.

Read a 3D NAND ONON etch filmstack through an *ultra-deep-superlattice-excavation* lens: a towering multi-micrometer periodic dielectric laminate where cryogenic surface condensation and multi-kilovolt ion acceleration unite to bore billions of defect-free atomic channels through hundreds of alternating oxide-nitride memory cells.

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