What Is an Etch Silicide Filmstack

An etch silicide filmstack (etch silicide etch filmstack) is an engineered nanoscale ohmic contact and barrier laminate structure formed at the source, drain, and gate interfaces of FinFET, gate-all-around (GAA) nanosheets, and complementary FET (CFET) devices. At scaled nodes ($N7$ to $A14$), contact resistance ($R_{\text{contact}}$) contributes over $50\%$ of the total transistor parasitic series resistance ($R_{\text{ext}}$), severely choking drive current ($I_{\text{on}}$) unless specific contact resistivity is reduced below $\rho_c < 1.5 \times 10^{-9}\text{ }\Omega\cdot\text{cm}^2$. To achieve this, refractory metal silicides and germanosilicides—such as titanium silicide ($TiSi_2$), nickel-platinum silicide ($Ni_{1-x}Pt_xSi$), or cobalt silicide ($CoSi_2$)—are integrated with ultra-thin titanium/titanium nitride ($Ti/TiN$) adhesion caps and inter-layer dielectric (ILD) contact trench matrices. Etching contact vias and trenches to land on this silicide filmstack represents one of the most perilous unit processes in middle-of-line (MOL) fabrication: the plasma must punch through 30 nm to 80 nm of dielectric ($SiO_2$, $Si_3N_4$, or low-$k$) and halt abruptly on an ultra-thin ($4\text{–}10\text{ nm}$) silicide layer without sputtering through the contact into the underlying source/drain junction, which would induce catastrophic junction leakage ($I_{\text{off}}$ spike) and destroy carrier mobility. At a high level, the architectural anatomy of an advanced silicide contact etch filmstack and its selective dry etch sequence looks like this:

A few principles are essential for understanding how silicide etch filmstacks are constructed, how metal-silicon phase thermodynamics dictate thermal stability, and why soft-landing plasma chemistries prevent junction punch-through:

Filmstack structural hierarchy and functional layers. An advanced middle-of-line silicide etch filmstack is arranged in five functional strata from top to bottom:
1. *Dielectric Passivation Matrix:* $40\text{ to }80\text{ nm}$ of middle-of-line inter-layer dielectric (MOL ILD), typically comprised of flowable chemical vapor deposition (FCVD) silicon dioxide ($SiO_2$) or silicon nitride ($Si_3N_4$) contact etch stop layers (CESL).
2. *Adhesion & Contact Barrier Cap:* $3\text{ to }5\text{ nm}$ of atomic layer deposited ($ALD$) titanium ($Ti$) and titanium nitride ($TiN$). This layer caps the underlying silicide, preventing silicide oxidation and acting as an adhesion promoter for tungsten ($W$) or cobalt ($Co$) contact plug fill.
3. *Silicide Ohmic Contact Layer:* $4\text{ to }10\text{ nm}$ of stoichiometric metal silicide or germanosilicide. In NMOS devices, titanium silicide ($TiSi_2$, C54 phase) or titanium germanosilicide ($TiSiGe$) provides a low Schottky barrier height for electrons ($\Phi_{Bn} \approx 0.05\text{ eV}$). In PMOS, nickel-platinum silicide ($Ni_{0.9}Pt_{0.1}Si$) provides an ultra-low barrier height for holes ($\Phi_{Bp} < 0.1\text{ eV}$). Platinum addition ($5\text{–}10\%$) suppresses agglomeration and raises the thermal degradation threshold above $650^\circ\text{C}$.
4. *Doped Epitaxial Semiconductor:* $20\text{ to }40\text{ nm}$ of phosphorus-doped silicon ($Si:P$) or boron-doped silicon-germanium ($Si_{0.7}Ge_{0.3}:B$) raised source/drain with active dopant concentrations exceeding $N_A, N_D > 5 \times 10^{20}\text{ cm}^{-3}$.
5. *Active Channel Junction:* Underlying crystalline silicon channel. If the silicide is punctured during contact etching or over-annealed, metal atoms diffuse into the depletion region, causing trap-assisted tunneling and severe leakage.

Plasma soft-landing kinetics and selectivity mechanisms. The physical challenge of opening contact holes onto a silicide filmstack centers on halting energetic plasma bombardment without stripping the 4–8 nm silicide layer:
- *Optical Emission Spectroscopy (OES) Endpoint Detection:* During the bulk dielectric etch, high RF bias power ($E_{\text{ion}} > 150\text{ eV}$) drives fast clearing of $SiO_2$ or $Si_3N_4$. High-speed spectrometers track the drop in $CN^*$ emission (at 388 nm from $Si_3N_4$ etching) or $CF_2^*$ emission (at 251 nm) and the rise of titanium or nitrogen optical peaks, pinpointing the moment the contact hole approaches the silicide interface.
- *Pulsed Bias Soft Landing:* Once endpoint is triggered, the RF bias generator transitions to low-duty-cycle pulsing ($1\text{–}5\text{ kHz}$ at $10\text{–}20\%$ duty cycle). In the bias-off periods, negative ions neutralize surface charge accumulation at the bottom of the deep contact via, eliminating charging-induced local electric fields that cause micro-trenching along feature corners. In the bias-on periods, ion energy is constrained below $30\text{ eV}$, well beneath the physical sputtering threshold of dense metallic silicide.
- *Non-Volatile Metal Fluoride Passivation:* In fluorocarbon plasmas ($C_4F_6/CH_2F_2/Ar$), volatile silicon tetrafluoride ($SiF_4$) gas is continuously desorbed while etching dielectric. However, upon encountering the metal silicide ($TiSi_2$ or $NiPtSi$), titanium and nickel fluorides ($TiF_3, NiF_2, PtF_4$) exhibit near-zero vapor pressures at standard wafer chuck temperatures ($40^\circ\text{C}\text{–}60^\circ\text{C}$). These species form an involatile surface passivation film that arrests chemical etching, delivering an effective etch selectivity of dielectric over silicide of $>30:1$. Total silicide consumption is restricted to $<1.0\text{ nm}$, leaving the ohmic contact intact.

Read a silicide etch filmstack through a *gatekeeper-junction-shield* lens: an atomic multi-material stack where high-speed fluorocarbon dielectric excavation is dialed down to a whisper by pulsed-plasma deceleration, halting cleanly on a thin metallic silicide skin to preserve pristine transistor junctions.