fill insertion

**Fill insertion** is the automated process of adding **dummy (non-functional) features** to empty areas of a chip layout to achieve **uniform pattern density** across each layer — ensuring consistent CMP planarization, etch uniformity, and stress distribution during manufacturing. **Why Fill Is Necessary** - **CMP Uniformity**: Chemical Mechanical Planarization removal rate depends on local pattern density. Without fill, low-density regions are over-polished, creating thickness variation. - **Etch Loading**: Etch rate can vary with local pattern density — uniform density reduces etch variation. - **Stress Balance**: Large empty regions surrounded by dense features can create differential stress — dummy features equalize stress. - **Foundry Requirements**: Every foundry mandates minimum and maximum pattern density ranges for each layer — fill is required to meet density specifications. **Types of Fill** - **Metal Fill**: Dummy metal shapes (typically small squares or rectangles) inserted in empty metal routing areas. - **Poly Fill**: Dummy polysilicon shapes in empty regions — required for poly CMP uniformity. - **Active (OD/Diffusion) Fill**: Dummy active area shapes — less common but required by some processes. - **Contact/Via Fill**: Sometimes required in regions with no functional contacts to maintain density. **Fill Rules and Constraints** - **Density Window**: The fill must bring local density (measured over a sliding window, typically 50–100 µm) within the specified range (e.g., 20–80% for metal layers). - **Spacing to Active Features**: Fill shapes must maintain minimum spacing from functional wires — to prevent capacitive coupling that could affect circuit timing. - **No Shorts**: Fill shapes must be isolated from functional nets — they are typically grounded, floating, or connected to a dedicated fill net. - **Exclude Regions**: Sensitive areas (analog circuits, RF structures, critical nets) may have fill exclusion zones where no fill is placed. **Fill Strategies** - **Floating Fill**: Fill shapes not connected to any net — simplest but can create antenna effects or charge up during plasma processing. - **Grounded Fill**: Fill shapes connected to ground — eliminates charging but requires routing ground connections to fill regions. - **Timing-Aware Fill**: Fill placement considers its capacitive impact on nearby signal wires — keeps fill away from timing-critical nets or accounts for fill capacitance during extraction. - **Density-Gradient Fill**: Varies fill density smoothly rather than creating sharp density transitions — better for CMP. **Fill in the Design Flow** - Fill insertion is typically one of the **last steps** before tapeout — after routing and optimization are complete. - **Post-Route Fill**: Insert fill, then re-extract parasitics to account for fill capacitance, and re-verify timing. - Some advanced flows perform **early fill estimation** during routing to pre-account for fill capacitance. Fill insertion is a **mandatory manufacturing requirement** — without it, CMP-induced thickness variation would make advanced-node fabrication impossible.