FinFET 2010s Walk Replacement Metal Gate Process Sequence on a Fin

# FinFET (2010s): Step 8 — Walk the Replacement-Metal-Gate Process Sequence on a Fin

## 1. Starting From a Sacrificial Dummy Gate

The RMG flow Step 7 motivated begins by patterning a sacrificial polysilicon dummy gate directly over the fin, in the same location the final gate will eventually occupy, then using that dummy gate as the self-aligned mask for source/drain implantation or epitaxial growth and the high-temperature activation anneal that follows.

## 2. Interlayer Dielectric Fill and Planarization

Once source/drain formation is complete, an interlayer dielectric is deposited around the dummy gate and chemically-mechanically polished down until the dummy gate's own top surface is exposed, creating a flat working surface without disturbing the source/drain regions the anneal already fixed in place.

## 3. Dummy-Gate Removal and Final Metal Fill

The sacrificial polysilicon is then selectively etched out, leaving an empty gate trench that exposes the fin's top and both sidewalls inside it. A high-k dielectric liner is deposited into this trench first, followed by one or more work-function metal layers tuned separately for NMOS and PMOS, and finally a low-resistance fill metal — all deposited at temperatures low enough to leave the earlier source/drain anneal, and the metal's own work function, undisturbed.

## 4. What This Step Does and Does Not Cover

This step walks the RMG sequence itself; it does not yet address how source/drain regions are shaped for the fin geometry specifically, including the merged-fin and raised-source/drain techniques Step 11 covers.

RMG's Sequencing Advantage: the Anneal Happens Before the Metal Exists process temperature experienced by the gate stack material, dummy-gate flow versus gate-first flow, over the process sequence gate-first: final metal gate stack exists through the full high-temperature anneal replacement gate: disposable dummy gate absorbs the anneal; final metal deposited only afterward the final metal's work function is never exposed to the activation anneal in the RMG sequence process generation advances left to right across this chart dummy-gate removal happens only after every high-temperature step is already complete high-k liner, split NMOS/PMOS work-function metals, and low-resistance fill go in last
The RMG Sequence, in Order four stages from dummy gate to finished metal gate, each protecting the stage before it DUMMY GATE + S/D ANNEAL sacrificial polysilicon masks source/drain formation and absorbs the high-temp anneal ILD FILL + CMP dielectric fill polished flush to the dummy gate's top, undisturbed source/drain beneath REMOVE + REFILL dummy etched out; high-k liner, work-function metals, and fill metal go in cold each stage exists specifically to keep the final metal gate's work function out of the high-temp anneal

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