finfet process integration

**FinFET Process Integration** is the **complete manufacturing flow for building three-dimensional fin-shaped field-effect transistors — from epitaxial substrate preparation through fin patterning, gate wrapping, and contact formation — requiring precise coordination of over 50 major process steps where the fin's narrow width (5-7nm at leading edge), tall aspect ratio (8-10:1), and three-dimensional geometry impose uniquely stringent requirements on every lithography, etch, deposition, and planarization step in the CMOS flow**. **Fin Formation** 1. **Mandrel Patterning**: For tight fin pitches (24-48nm), SADP or SAQP creates the fin pattern. Mandrels are patterned by lithography, then sidewall spacers define the final fin pitch at 2x or 4x the lithographic pitch. 2. **Silicon Etch**: Anisotropic reactive ion etch transfers the pattern into the silicon, creating tall, thin fins. Fin height: 40-50nm. Fin width: 5-7nm at advanced nodes. The etch must produce vertical sidewalls with <1nm roughness — any width variation directly modulates threshold voltage. 3. **STI Recess**: Oxide is deposited to fill between fins, then recessed by controlled etch to expose the upper portion of each fin. The recess depth determines the electrically active fin height — this is a critical dimension with ±1nm tolerance. **Gate Integration** 4. **Dummy Gate**: Polysilicon dummy gate is deposited conformally over the fins and patterned perpendicular to the fins. Where the gate crosses a fin, it wraps over the fin top and both sidewalls — the three-sided gate contact that gives FinFETs their electrostatic advantage. 5. **Spacer Formation**: Silicon nitride spacers are formed on the gate sidewalls by deposition and etch-back. The spacer width defines the distance between the gate edge and the source/drain regions. 6. **S/D Recess and Epitaxy**: Fins are recessed in the source/drain regions. Epitaxial SiGe (PMOS) or Si:P (NMOS) is grown, merging between adjacent fins to form a continuous source/drain contact. 7. **RMG**: Dummy gate is removed and replaced with HfO₂ + metal gate (as described in the HKMG entry). **Contact Formation** 8. **S/D Contact**: Sacrificial dielectric over the source/drain is etched to form contact trench. A silicide (TiSi or NiSi) is formed on the S/D epitaxy surface. Barrier (TiN) and metal fill (Co, W, or Ru) complete the contact. Contact resistance — especially the interface between metal and heavily-doped semiconductor — is a primary performance limiter at advanced nodes. 9. **Gate Contact**: Separate patterning opens contacts to the metal gate, connecting to the local interconnect. **Variability and Yield** Fin width variation of ±1nm causes ~10% drive current variation (because the entire fin is the channel — width modulation changes the effective channel width). Fin height variation and gate length variation each contribute additional variability. The combined parametric spread determines SRAM Vmin and logic timing margins. Tight process control (±0.5nm) on these dimensions is the primary yield lever for FinFET manufacturing. FinFET Process Integration is **the three-dimensional manufacturing challenge that redefined what "building a transistor" means** — a vertical fin protruding from the silicon surface, wrapped by a gate on three sides, with epitaxial contacts and atomic-layer gate dielectrics, all controlled to sub-nanometer precision across 300mm wafers.