GIDL gate induced drain leakage
**Gate-Induced Drain Leakage (GIDL)** is the **off-state leakage mechanism where a strong electric field in the gate-to-drain overlap region causes band-to-band tunneling (BTBT), generating electron-hole pairs that contribute to drain leakage current** — becoming increasingly significant at advanced nodes where thin gate oxides and high channel doping create the intense fields needed for quantum mechanical tunneling.
**Physical Mechanism**: When the transistor is off (V_GS = 0 or negative for NMOS), the gate-to-drain overlap region experiences a strong vertical electric field (gate at 0V while drain is at V_DD). This field bends the energy bands in the silicon so severely that the valence band on one side aligns with the conduction band on the other within a tunneling distance (~5-10nm). Electrons tunnel from the valence band to the conduction band (band-to-band tunneling), creating electron-hole pairs. Electrons flow to the drain (adding to I_off), holes flow to the body (creating body current).
**GIDL Dependence**:
| Parameter | Effect on GIDL | Reason |
|-----------|---------------|--------|
| Thinner gate oxide | Increases GIDL | Stronger field for same V_DG |
| Higher drain doping | Increases GIDL | Steeper band bending |
| Higher |V_DG| | Exponentially increases GIDL | Stronger tunneling field |
| Higher temperature | Increases GIDL (moderately) | Enhanced thermal generation |
| Gate-drain overlap | Increases GIDL | Larger tunneling area |
**GIDL vs. Other Leakage Components**: Total off-state drain current (I_off) comprises: **subthreshold leakage** (diffusion over the barrier — exponential in V_th), **GIDL** (BTBT at the drain under the gate — exponential in field), **junction leakage** (reverse-biased S/D junction — smaller), and **gate leakage** (tunneling through the gate oxide — addressed by high-k). At high V_th (low subthreshold leakage), GIDL often dominates I_off because it is independent of threshold voltage.
**GIDL in DRAM**: GIDL is particularly critical for DRAM retention. The storage capacitor charge slowly leaks through the access transistor's off-state current. Since DRAM transistors are designed with very high V_th (to minimize subthreshold leakage), GIDL becomes the dominant leakage path. DRAM employs negative word-line (negative V_GS in off-state) to suppress subthreshold leakage, but this actually increases GIDL by increasing |V_DG|. The optimal negative word-line voltage balances subthreshold and GIDL.
**GIDL Mitigation**: **Reduce gate-drain overlap** (but increases series resistance); **use lightly doped drain (LDD)** (lowers the maximum field at the drain edge); **thicker oxide at drain overlap** (asymmetric transistor, adds process complexity); **lower drain/body doping** at the overlap (reduces band bending); **negative voltage optimization** (balance gate voltage in off-state to minimize total I_off = subthreshold + GIDL).
**GIDL in FinFET and GAA**: The thin body of FinFET and nanosheet devices reduces GIDL compared to bulk planar devices because the fully-depleted thin channel inherently limits band bending. However, the smaller volume also concentrates the field, and the use of high-performance epi S/D with very high doping can increase GIDL at the channel/S/D junction.
**Gate-induced drain leakage illustrates how quantum mechanical tunneling increasingly governs transistor behavior at nanometer scales — a phenomenon that was negligible at larger geometries but now sets fundamental limits on the minimum leakage power achievable in the off-state, particularly for memory and ultra-low-power applications.**