hkmg gate

**High-k Metal Gate (HKMG)** is **the revolutionary gate stack technology that replaced SiO₂/polysilicon with high-dielectric-constant materials (HfO₂, HfSiON) and metal gate electrodes — enabling continued gate dielectric scaling below 1nm equivalent oxide thickness (EOT) while controlling gate leakage current, eliminating polysilicon depletion effects, and maintaining proper threshold voltages for both NMOS and PMOS transistors at 45nm technology nodes and beyond**. **High-k Dielectric Materials:** - **Hafnium Oxide (HfO₂)**: dielectric constant k≈25 (vs SiO₂ k=3.9) enables 5-7× thicker physical films for the same capacitance; physical thickness 2-3nm provides EOT of 0.8-1.2nm with dramatically reduced tunneling leakage (100-1000× lower than equivalent SiO₂) - **HfSiON Alloys**: hafnium silicate oxynitride provides intermediate k values (12-20) with better interface quality and thermal stability than pure HfO₂; nitrogen incorporation suppresses boron penetration and reduces oxygen vacancy defects - **Interface Layer**: thin SiO₂ or SiON interlayer (0.3-0.6nm) between silicon and high-k is critical for interface quality; this interfacial layer limits EOT scaling but provides low interface trap density (Dit < 10¹¹ cm⁻²eV⁻¹) essential for mobility and reliability - **Deposition Methods**: atomic layer deposition (ALD) at 250-350°C provides conformal, uniform high-k films with precise thickness control (±0.1nm); alternating HfCl₄/H₂O or TDMAH/H₂O precursor pulses build film one atomic layer at a time **Metal Gate Electrodes:** - **Work Function Engineering**: NMOS requires low work function metals (4.0-4.3eV) near silicon conduction band; PMOS requires high work function (4.9-5.2eV) near valence band; dual metal gates provide proper threshold voltages without heavy channel doping - **NMOS Metals**: TiN, TaN, or TiAlN with aluminum content tuning work function; Al incorporation lowers work function by 0.1-0.3eV per 10% Al; typical composition Ti₀.₆Al₀.₄N provides 4.2eV work function - **PMOS Metals**: TiN with controlled nitrogen content, or TaN/TiN stacks; oxygen incorporation during high-k deposition shifts TiN work function higher; some processes use separate PMOS metal deposition (MoN, RuO₂) for optimal work function - **Gate Fill**: after thin work function metal liner (3-5nm), tungsten CVD fills the gate trench; W provides low resistivity (10-15 μΩ·cm) and excellent gap-fill for high-aspect-ratio gates at advanced nodes **Integration Schemes:** - **Gate-First**: deposit high-k/metal gate, pattern gates, then perform source/drain activation anneals; metal gate must survive 1000-1050°C anneals — limits metal choices and causes work function shifts from thermal budget - **Gate-Last (Replacement Gate)**: deposit sacrificial polysilicon gate, complete source/drain processing with full thermal budget, remove polysilicon, deposit high-k/metal gate in the trench; decouples gate materials from thermal processing but adds complexity - **High-k First, Metal Gate Last**: deposit high-k early (survives thermal budget well), use polysilicon placeholder, replace with metal gate after anneals; hybrid approach balancing interface quality and process simplicity - **Threshold Voltage Tuning**: lanthanum (La) incorporation in high-k shifts NMOS Vt by -0.2 to -0.4V; aluminum (Al) shifts PMOS Vt by +0.2 to +0.3V; enables multi-Vt devices (low-Vt, standard-Vt, high-Vt) for power-performance optimization **Performance Impact:** - **Leakage Reduction**: gate leakage reduced 100-1000× compared to SiO₂ at equivalent EOT; enables EOT scaling to 0.7nm at 22nm node without excessive off-state leakage (Ioff < 100pA/μm) - **Mobility Degradation**: high-k materials introduce remote phonon scattering and Coulomb scattering from charged defects; electron mobility reduced 10-20%, hole mobility reduced 5-15% compared to SiO₂; strain engineering partially compensates - **Reliability Improvements**: elimination of polysilicon depletion adds 0.2-0.3nm to effective gate capacitance; metal gates eliminate boron penetration issues that plagued ultra-thin SiO₂; bias temperature instability (BTI) becomes the dominant reliability concern - **Variability**: high-k grain structure and metal gate work function variations contribute to threshold voltage variability; σVt increases 10-20mV compared to SiO₂/poly gates; requires statistical design methods at advanced nodes High-k metal gate technology represents **the most significant gate stack innovation in CMOS history — enabling the continuation of Moore's Law scaling beyond the fundamental limits of SiO₂ dielectrics, with HfO₂-based gate stacks now standard in every advanced logic process from 45nm to 3nm nodes and beyond**.