Hmos 1978 Step 11 Intel Commercial Context 8086 Second Source

# Step 11 — Place HMOS in Intel's Own 1978 Commercial Context

## 1. Ask Why Intel Needed a Faster NMOS Process at All, Rather Than Simply a Better One

Steps 1 through 10 treated HMOS as a device-physics and process problem: a fixed supply rail, a climbing channel field, a depletion-load redesign, a thinner oxide, a second polysilicon layer. None of that explains why Intel committed engineering resources to this specific set of tricks in 1978 rather than, say, waiting for CMOS to mature or simply shrinking the existing 8080-generation process incrementally. The answer sits one level up, in the microprocessor market Intel was competing in that year.

The 8080, introduced in 1974, was losing ground on raw throughput by 1978, and the architecture Intel wanted to ship next — the 16-bit 8086 — needed a process that could clock substantially faster than the 8080's silicon-gate NMOS baseline without changing the 5 V system-level compatibility every existing board, power supply, and TTL peripheral chip assumed. That last constraint is exactly Step 1's fixed-voltage boundary, restated as a business requirement rather than a physics one: redesigning the voltage rail was not an option Intel's customers would tolerate, because it would have broken every existing 8080-era system and peripheral family in one stroke.

1978: Three Microprocessors Competing on Clock Speed, Not Architecture Alone Intel needed a process answer, not just a wider data bus INTEL 8086 16-bit, HMOS process needs clock speed the 8080-era silicon-gate process cannot deliver must keep 5 V rail board, supply, TTL periphery all assume it answer: HMOS process not a new architecture rule ZILOG Z8000 16-bit, direct competitor launched the same year, forcing a direct clock speed comparison a window where delay cost market share MOTOROLA 68000 16/32-bit, HMOS-class process a separate design team reaching the same oxide and implant conclusions in parallel confirms the constraint was industry-wide, not Intel-specific THE COMMERCIAL READING OF STEP 1'S CONSTRAINT a fixed 5 V rail was not a physicist's convenience — it was every existing board, power supply, and TTL peripheral already shipped, which no vendor could unilaterally break process engineering was the only lever left that did not require the customer base to change hardware

## 2. Trace the Decision From Architecture Choice to Process Choice

Intel's architects fixed the 8086's instruction set and 16-bit data path largely independent of process; the process group's job was to make that architecture clock fast enough, on time, without forcing a system-level voltage change. Two paths existed in principle. The first was to wait for CMOS, which Step 9 already showed was denser in theory but, in 1978, carried a well-isolation, latchup-margin, and mask-count cost that made it slower to bring to the volume and yield Intel needed for a flagship product launch. The second was to push the existing NMOS process family harder — exactly what HMOS did.

The commercial logic was not "HMOS is the best possible process"; it was "HMOS is the process that gets a competitively clocked 16-bit part to market on a schedule CMOS could not yet match, on a voltage rail nobody has to redesign around." That is a time-to-market and compatibility argument, not a pure performance argument, and it explains a detail Steps 1 through 10 treat only as a constraint: why Intel tolerated the static power and reliability costs documented in Steps 13 and 14 of this extension rather than switching device families outright. Switching was available in principle. It was not available on the 8086's schedule.

Two Paths From the Same 1978 Starting Point PATH A — WAIT FOR CMOS denser in theory (Step 9) well isolation, latchup margin, mask count not yet volume-ready misses the 8086 launch window PATH B — PUSH NMOS (HMOS) depletion load, thin oxide, second poly layer (Steps 2-6) keeps the 5 V rail unchanged meets the schedule, accepts the cost INTEL CHOSE PATH B FOR THE 8086 not because HMOS was the better long-run technology (Step 9 already says it was not), but because it was the technology that could ship a competitively clocked part on schedule this is why Steps 13-14's power and reliability costs were tolerated, not avoided

## 3. Place This Step in the Extension's Own Lineage

This step does not revisit the device physics Steps 1 through 10 already established; it supplies the commercial motive those steps assumed without stating. The 8086's need for a faster clock at an unchanged 5 V rail is the business-level restatement of Step 1's fixed-voltage constraint, and Intel's choice to push NMOS rather than wait for CMOS is the business-level restatement of Step 9's observation that CMOS was denser in theory but not yet ready in practice. Step 12 turns from why Intel made this choice to what the 1978 lithography equipment floor would actually let any engineer do about it — the physical limits on mask alignment and feature placement that shaped which of the scaling tricks in Steps 2 through 6 were even buildable at volume yield.

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