Hmos 1978 Step 12 Confront Lithography Alignment Tolerance Limits

# Step 12 — Confront the 1978 Lithography Floor That Bounded Every Scaling Trick Above

## 1. Separate the Device-Physics Argument From the Equipment Argument

Steps 1 through 8 argued in the language of fields, currents, and oxide thickness, as if any dimension could be cut the moment the physics justified it. In 1978, mask-making and wafer alignment equipment set a harder floor under several of those dimensions than the device physics alone did, and the second-polysilicon-layer redesign of Step 6 in particular existed inside that floor, not outside it. Contact and proximity aligners — the dominant exposure tools before projection aligners reached volume production later in the decade — printed a mask pattern by placing it in close contact with, or a small gap above, the photoresist-coated wafer, and registering each new mask layer against the pattern already on the wafer by eye-assisted optical alignment, repeated at every one of the now nine mask levels Step 6 required.

Each alignment carries a tolerance, and tolerances accumulate layer over layer. A design rule that assumes perfect registration between the first polysilicon gate and the second polysilicon interconnect layer is not implementable on a contact aligner; the layout has to budget extra spacing — "alignment margin" — around every feature that a misregistered second-poly layer could otherwise short or open. That margin is area the device-physics argument in Step 6 never had to account for, because Step 6 reasoned about layout congestion in the ideal case of perfect registration.

Alignment Tolerance Accumulates Across Nine Mask Levels contact/proximity aligner registration error per layer, Step 6's nine-mask HMOS flow LAYER 1 (diffusion) — registered against nothing, zero accumulated error LAYER 4 (poly 1 gate) — three alignments deep, modest accumulated error LAYER 7 (poly 2 interconnect, Step 6) — six alignments deep, significant accumulated error LAYER 9 (final metal/contact) — eight alignments deep, largest accumulated error registration error climbs with layer depth; layout margin must budget for the worst layer, not the average WHAT STEP 6'S IDEAL-CASE ACCOUNTING LEFT OUT the density gain from a second poly layer assumed perfect registration between poly 1 and poly 2 real contact-aligner registration error forces an alignment-margin tax on exactly that gain the net density win still holds — it is smaller than Step 6's idealized layout implied

## 2. Quantify What the Margin Actually Costs, and Why Projection Aligners Were Not Yet the Answer

A typical contact/proximity alignment tolerance in volume production around 1978 ran on the order of one to two microns per layer, worst case, after accounting for mechanical registration repeatability, wafer bow, and mask-to-wafer gap variation in proximity mode. Over a flow with multiple critical alignments between poly 1, poly 2, and the contact/metal layers above them, worst-case accumulated misregistration could reach several microns — not small next to the roughly 3.5 micron channel length Step 7 reports for first-generation HMOS. A device whose most aggressive dimension is itself a few microns cannot treat a multi-micron alignment tolerance as negligible; it has to design the layout around it, which is exactly the "alignment margin" cost named above.

Projection aligners, which image a mask onto the wafer through a lens rather than placing it in contact, reduce mask wear and improve some registration error sources, but in 1978 they were still reaching the throughput, field size, and resolution needed to displace contact/proximity tools in high-volume logic production outright; adoption was uneven across the industry through the end of the decade. HMOS's process engineers in Steps 2 through 6 of the base series were therefore not choosing among scaling tricks in a vacuum — they were choosing among the subset of tricks whose layout margins a contact/proximity-aligner production line could actually hold at the yield a flagship microprocessor launch required.

Alignment Tolerance Against the Device's Own Smallest Dimension CONTACT / PROXIMITY ALIGNER worst-case registration error ~1-2 µm per layer accumulated over 6-8 critical alignments: several µm worst case dominant tool in volume production, 1978 CHANNEL LENGTH, FIRST-GEN HMOS from Step 7's own measurement ~3.5 µm a multi-micron alignment error is not negligible against this scale projection aligners not yet dominant at this volume THE EQUIPMENT FLOOR SHAPED, NOT JUST CONSTRAINED, THE PROCESS CHOICES ABOVE every scaling trick in Steps 2 through 6 had to leave layout margin for this error before it could claim the density or speed gain the pure device-physics argument promised

## 3. Place This Step in the Extension's Own Lineage

This step does not change any device-physics conclusion from Steps 1 through 10 — it bounds the layout margin those conclusions had to assume. The second-polysilicon-layer redesign of Step 6 remains a net density win, but a smaller one than an ideal-registration accounting implies, once the contact/proximity-aligner tolerance budget documented here is subtracted. Step 13 turns from the equipment that built HMOS to the operating cost of the device it built: the static power the ratioed depletion-load inverter draws whenever its output sits LOW, a cost every step so far has mentioned in passing and none has yet quantified on its own terms.

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