local interconnect routing
**Middle-of-Line (MOL) Integration** is the **process module that bridges the gap between front-end transistor fabrication (FEOL) and back-end metal interconnects (BEOL) — encompassing the critical contact and local interconnect structures (trench silicide, contact plugs, and local wiring) that connect individual transistors to the first metal routing layer, where the dimensions are smallest, the aspect ratios are highest, and the resistance per unit length is greatest in the entire chip**.
**MOL Structure and Components**
- **Trench Silicide (TS)**: Metal silicide formed in trenches over the source/drain regions to create low-resistance ohmic contacts. Extends along the gate-pitch direction to connect adjacent source/drain regions.
- **Contact (CT/CA)**: Vertical plugs connecting the trench silicide (or gate metal) to the first metal level (M0 or local interconnect). High-aspect-ratio holes (>10:1) at sub-20nm diameter filled with tungsten or cobalt.
- **Contact Over Active Gate (COAG)**: Placing contacts directly over the transistor gate electrode instead of at the gate ends — reduces cell height by eliminating the gate contact extension area. Requires self-aligned contacts with precise dielectric barriers between gate contact and source/drain.
**Key Challenges at MOL**
- **Aspect Ratio**: Contacts at 3nm node have diameters of 12-18nm with depths of 80-120nm — aspect ratios of 5:1 to 10:1. Filling these with conducting metal without voids is extremely difficult.
- **Contact Resistance**: As contact area shrinks (proportional to dimension²), resistance increases quadratically. MOL contact resistance is now the dominant parasitic in transistor performance.
- **Self-Alignment Requirements**: At gate pitches below 48nm, contacts cannot be reliably placed between gates by lithographic overlay alone. Self-aligned contact (SAC) schemes use etch-selective dielectric caps on the gate to prevent gate-to-contact shorts even when the contact is misaligned.
**Metal Fill Evolution**
| Generation | Contact Fill Metal | Barrier/Liner | Motivation |
|------------|-------------------|---------------|------------|
| 45-22nm | Tungsten (W) | TiN/Ti | Low cost, reliable CVD fill |
| 14-7nm | Cobalt (Co) | TiN | Lower resistivity in narrow dimensions, no fluorine attack |
| 5-3nm | Ruthenium (Ru) | Barrierless | Minimal grain boundary scattering, no liner needed |
| Sub-3nm | Molybdenum (Mo) | Barrierless | Lowest resistivity at <10nm dimension, ALD-fillable |
**Integration with Gate-All-Around**
Nanosheet GAA transistors create unique MOL challenges: contacts must reach source/drain epitaxial regions wrapped around stacked nanosheets, inner spacers must electrically isolate gate from source/drain at each nanosheet level, and the 3D geometry demands highly conformal etch and deposition processes.
MOL Integration is **the critical dimensional chokepoint of advanced CMOS** — where the smallest features in the entire chip must be fabricated, filled, and connected with near-zero resistance and near-zero defectivity to enable the transistor performance that the front-end engineering delivers.