middle of line
**Middle of Line (MOL)** is the **fabrication module between the transistor (FEOL) and the global wiring (BEOL) that creates the local contacts and interconnects connecting transistors to the first metal layer** — a critical bottleneck in advanced CMOS where contact resistance and dimensions determine how effectively nanoscale transistors can deliver current to the interconnect stack.
**FEOL → MOL → BEOL**
| Module | Creates | Layers |
|--------|---------|--------|
| FEOL | Transistors (gate, S/D, channel) | Wells, oxide, poly/metal gate |
| MOL | Local contacts and interconnects | Contact (CA/CB), M0A/M0B |
| BEOL | Global wiring | M1-M15+ metal levels |
**MOL Components**
- **Source/Drain Contact (CA or TS)**: Tungsten or cobalt plug landing on silicided S/D region.
- **Gate Contact (CB)**: Contact to the metal gate electrode — must not short to adjacent S/D.
- **Via-0 (V0)**: Connects MOL contacts to the first metal level (M1).
- **Local Interconnect (M0A/M0B)**: Short-range routing within a standard cell — connects adjacent transistors without going up to M1.
**MOL Scaling Challenges**
- **Contact Resistance**: As contact area shrinks from 64 nm² (8x8nm) to 25 nm² (5x5nm):
- Rc ∝ $\frac{\rho_c}{A_{contact}}$ — resistance increases inversely with area.
- At 3nm node: Contact resistance dominates total parasitic resistance (> 50%).
- **Contact-to-Gate Spacing**: Must avoid shorting CA to CB — self-aligned contacts (SAC) with dielectric caps essential.
- **Material Transition**: Tungsten (W) plugs being replaced by cobalt (Co) and ruthenium (Ru) for lower resistivity at nanoscale dimensions.
**Self-Aligned Contact Architecture**
- Dielectric cap deposited on top of metal gate before contact etch.
- Contact etch stops on cap — allows contact landing with near-zero spacing to gate.
- Without SAC: lithographic alignment would require larger spacing → larger cells → lower density.
**MOL Innovation at Advanced Nodes**
- **Contact-over-Active-Gate (COAG)**: Allows gate contact to land directly over the channel — eliminates dead space, shrinks cell height.
- **Selective Deposition**: Deposit barrier/liner only where needed — reduces plug resistance.
- **Wrapround/Epi Contact**: For GAA nanosheets, contacts must wrap around the channel for maximum S/D contact area.
Middle of line is **the most resistance-critical module in advanced CMOS** — as transistors shrink to sub-3nm dimensions, MOL contact engineering determines whether the inherent speed of nanoscale transistors can be delivered to the chip's wiring network.