mol
**MOL (Middle of Line)** is the **transitional fabrication phase between transistors and metal interconnects** — creating the critical contact plugs and local interconnect structures that physically connect FEOL transistor terminals (gate, source, drain) to the first layers of the BEOL metal routing network.
**What Is MOL?**
- **Definition**: The process steps that create the first electrical connections from the transistor's gate, source, and drain contacts up to the first metal layer (M1) — bridging FEOL device fabrication and BEOL metallization.
- **Structures**: Contact plugs (tungsten or cobalt bars filling contact holes), local interconnects, and trench contacts that connect transistor terminals to M1 routing.
- **Scale**: MOL features are the smallest and most challenging contacts in the chip — contact holes as small as 10-15nm at leading-edge nodes.
**Why MOL Matters**
- **Bottleneck Region**: MOL contacts carry all current between transistors and interconnects — high contact resistance directly degrades transistor performance.
- **Yield-Critical**: Contact etch and fill at sub-20nm dimensions are among the most challenging and yield-limiting process steps in semiconductor manufacturing.
- **Performance Scaling**: As transistors shrink, MOL contact resistance becomes a larger fraction of total resistance — MOL innovation is essential for continuing Moore's Law benefits.
- **Material Innovation**: The shift from tungsten to cobalt and ruthenium for MOL contacts is one of the biggest material changes in modern semiconductor manufacturing.
**Key MOL Process Steps**
- **Contact Etch**: High-aspect-ratio etch through dielectric to expose transistor source/drain and gate surfaces — requires extreme precision to avoid shorting adjacent contacts.
- **Pre-Clean**: Surface treatment to remove native oxide from silicon/silicide surfaces before metal deposition — critical for low contact resistance.
- **Barrier Deposition**: Thin TiN or TaN liner prevents metal diffusion and improves adhesion.
- **Metal Fill**: Contact holes filled with tungsten (W), cobalt (Co), or ruthenium (Ru) using CVD or ALD processes.
- **CMP**: Chemical mechanical polishing removes excess metal and planarizes the surface for M1 patterning.
**MOL Material Evolution**
| Node | Contact Metal | Barrier | Key Challenge |
|------|-------------|---------|---------------|
| 28nm+ | Tungsten (W) | TiN | Standard |
| 14-10nm | Tungsten (W) | TiN | High aspect ratio |
| 7-5nm | Cobalt (Co) | TiN | Resistance at small dimensions |
| 3nm | Cobalt/Ruthenium | Thin TaN | Contact resistance dominance |
| 2nm+ | Ruthenium (Ru) | Barrierless | Eliminate barrier resistance |
**MOL vs. FEOL vs. BEOL**
- **FEOL**: Builds transistors (gate, source, drain) — device engineering.
- **MOL**: Connects transistor terminals to the first metal layer — contact engineering.
- **BEOL**: Routes signals and power across the chip — wiring engineering.
- **Trend**: MOL is increasingly recognized as a separate and critical process module, no longer lumped into either FEOL or BEOL.
**Equipment and Vendors**
- **Contact Etch**: Lam Research, Tokyo Electron — high-aspect-ratio dielectric etch.
- **Metal Fill**: Applied Materials (Endura), Lam Research — CVD/ALD tungsten and cobalt.
- **CMP**: Applied Materials (Reflexion) — contact plug planarization.
- **ALD**: ASM International, Tokyo Electron — atomic layer deposition for thin barriers and liners.
MOL is **the most challenging dimensional bottleneck in semiconductor manufacturing** — where the smallest features in the entire chip must simultaneously achieve low resistance, high reliability, and perfect alignment to connect nanoscale transistors to the metal wiring network above.