middle of line mol process

**Middle-of-Line (MOL) Processing** is the **set of CMOS fabrication steps bridging the front-end-of-line (transistor fabrication) and back-end-of-line (multilevel metallization) — forming the local contacts that connect transistor source, drain, and gate terminals to the first metal routing layer, where the extreme density and tight overlay requirements of MOL make it the most dimensionally challenging module in the entire process flow, with contact dimensions of 10-20nm at sub-3nm nodes**. **What MOL Includes** 1. **Source/Drain Contacts (TSCL — Trench Silicide Contact Liner)**: Etching contact trenches through the interlayer dielectric (ILD0) to the source/drain epitaxy. Forming a silicide (TiSi₂) at the metal-semiconductor interface for low contact resistance. Depositing barrier metal (TiN) and filling with conductor (Co, W, or Ru). 2. **Gate Contact**: Separate contact to the metal gate electrode. Must be isolated from adjacent S/D contacts by the gate spacer — at tight dimensions, this isolation margin is <5nm. 3. **Contact Over Active Gate (COAG)**: At advanced nodes, the gate contact can be placed directly over the active transistor area (rather than extending the gate past the active region). COAG saves 20-30% of standard cell area but requires extreme patterning precision to avoid shorting the gate contact to the adjacent S/D contact. 4. **Local Interconnect (LI / M0)**: The first routing layer that makes short-distance connections — connecting source to source, gate to drain (for series transistors), and other local routing. Patterned in the same module as MOL contacts. **MOL Challenges** - **Contact Resistance**: The interface between the metal contact and the semiconductor (source/drain) contributes contact resistance Rc that directly limits transistor performance. Rc depends on silicide work function, semiconductor doping concentration, and contact area. At advanced nodes, Rc exceeds channel resistance — making MOL the performance bottleneck. - Mitigation: Heavy S/D doping (>2×10²¹ cm⁻³), optimized silicide (Ti-based for low barrier height), contact area enhancement (wrapping contact around all exposed S/D surfaces). - **Aspect Ratio**: Contact holes at sub-20nm diameter with 50-80nm depth (AR = 3-5:1) are difficult to etch cleanly, fill without voids, and planarize without residue. - **Self-Aligned Contacts (SAC)**: The gate cap (SiN) protects the gate from being exposed during S/D contact etch. The etch must be selective to the cap material (>50:1 selectivity) — any cap erosion risks gate-to-S/D shorts. - **Overlay**: Gate contact must land precisely on the gate without touching S/D regions. S/D contacts must land on S/D without touching the gate. The margin for error is <3nm, requiring state-of-the-art overlay from the lithography scanner. Middle-of-Line is **the bottleneck between the transistor and the wire** — where the three-dimensional complexity of modern transistors meets the two-dimensional reality of lithographic patterning, creating the most alignment-critical contacts in the entire chip at dimensions that push every process tool to its limit.