metal gate workfunction tuning
**Metal Gate Work Function Tuning and Dipole Engineering** is the **threshold voltage (VT) adjustment methodology for high-k/metal gate (HKMG) transistors that uses ultra-thin dipole layers at the high-k/interfacial oxide interface or within the high-k stack to shift the effective work function and achieve target VT values** — enabling multiple VT flavors (high-VT for low leakage, standard-VT for balanced PPA, low-VT for high performance) on a single wafer without requiring separate implants through the high-k gate dielectric.
**Why Conventional VT Tuning Is Difficult in HKMG**
- Traditional VT adjustment: change channel doping (body implant) → difficult when channel is undoped (fully depleted, FinFET, GAA).
- Metal gate work function set by metal composition → limited tunability once metal is chosen.
- High-k dielectric has fixed charges that shift VT unpredictably.
- **Solution**: Insert dipole-forming layers at the high-k/SiO₂ interface → shift flat-band voltage → shift VT precisely.
**Dipole Engineering Mechanism**
- A dipole forms when elements with different electronegativities meet at an interface.
- **La₂O₃ (Lanthanum oxide) dipole**:
- Deposited at SiO₂/high-k interface before HfO₂ deposition.
- La diffuses into interfacial SiO₂ during anneal → La-O dipole points toward Si → NEGATIVE fixed charge → VT shifts NEGATIVE (ΔVT = −0.2 to −0.5V).
- Use: NMOS VT reduction (high-performance NMOS).
- **AlN / Al₂O₃ (Aluminum oxide) dipole**:
- Al at interface → POSITIVE dipole charge → VT shifts POSITIVE (+0.2 to +0.4V).
- Use: PMOS VT increase or NMOS high-VT.
**VT Flavors via Dipole Engineering**
| Flavor | Dipole Used | VT Shift | Application |
|--------|-----------|---------|-------------|
| LVT (Low VT, High speed) | La₂O₃ on NMOS | −0.3 to −0.5V | Critical path logic |
| SVT (Standard VT) | No dipole | Baseline | General logic |
| HVT (High VT, Low leakage) | Al₂O₃ or TiN cap tuning | +0.2 to +0.4V | Sleep transistors, SRAM |
| ULVT (Ultra Low VT) | High La dose | −0.5 to −0.8V | Ultra-high performance |
**Dipole Process Integration**
```
1. Interfacial oxide (SiO₂) grown on Si channel (~1–1.5 nm)
2. Dipole layer deposition: ALD La₂O₃ or Al₂O₃ (0.3–1 nm)
3. Capping layer (TiN, 1–2 nm) to stabilize dipole
4. HfO₂ high-k deposition (ALD, 1.5–2 nm)
5. PDA (Post Deposition Anneal) 500–700°C → activates dipole
→ La/Al diffuses into interfacial SiO₂ → forms interface dipole
6. Work function metal deposition (TiN, TaN, Al-rich TiAlC)
7. Gate fill metal (W, Ru, Co)
```
**Work Function Metal Stack for VT Tuning**
- Beyond dipoles, WF metal thickness and composition also tune VT.
- Thinner TiN over HfO₂ → different effective WF (Fermi level pinning varies with thickness).
- Al-doped TiAlC: Al shifts WF toward Si conduction band → NMOS LVT.
- TaN + TiN: WF near Si mid-gap → used for balanced HVT NMOS or LVT PMOS.
**Dipole Stability**
- La and Al at SiO₂/HfO₂ interface must remain stable through all subsequent process steps (S/D anneal, contact formation, 400°C forming gas).
- La diffusion can continue at high temperature → risk of over-diffusing into channel → EOT growth → VT shift.
- Process control: Carefully control PDA temperature and dipole layer thickness.
**EOT Penalty**
- Dipole layer adds ~0.1–0.3 nm equivalent oxide thickness (EOT) → slight reduction in gate control.
- Engineers balance VT target vs. EOT penalty when choosing dipole dose.
Metal gate work function tuning via dipole engineering is **the precision VT pharmacology of advanced HKMG transistors** — by delivering four or more VT flavors through atomic-scale interface chemistry rather than physical implants through the gate dielectric, dipole engineering enables SoC designers to optimize every circuit block independently for performance, leakage, or area without process changes or mask additions.