Microprocessor 1971 Step 12 Faggin Individual Contribution Silicon Gate Implementation
# Name the Individual Contributions: Hoff's Architecture, Mazor's Instruction Set, Faggin's Silicon
## 1. Three Distinct Jobs Behind One Chip, Not One Person's Design
This series has so far described the 4004 as a set of engineering decisions — word width, bus multiplexing, decoder structure, arithmetic design — without separating who made each decision. The historical record attributes three distinct, non-overlapping contributions to three named engineers at Intel, and collapsing them into a single undifferentiated "Intel designed the 4004" understates how specialized each job actually was.
Ted Hoff proposed the architectural reorganization this series' Step 1 describes: replace Busicom's fixed-function chip set with a general interpreter reading instructions from memory. Stanley Mazor, working with Hoff, turned that architectural proposal into an actual instruction set — the specific operations, encodings, and addressing behaviors a programmer would use, a job distinct from deciding that instructions should exist at all. Federico Faggin, who joined Intel after both of those decisions were already underway, did the job neither Hoff nor Mazor was positioned to do: translate an instruction set specification into a working silicon-gate PMOS layout that could actually be fabricated, including random-logic circuit design techniques Intel had not previously used in a chip this complex.
## 2. What "Silicon-Gate Implementation" Actually Required, Beyond Step 4's Decoder
Step 4 of this series describes the instruction decoder in terms of what it does — turning a stored bit pattern into control signals — without describing the layout discipline that made a decoder of that complexity fabricable on 1971 equipment at all. Faggin's specific technical contribution was a random-logic design methodology for silicon-gate PMOS: rather than hand-laying every transistor as an isolated element, he developed systematic approaches to bootstrap load circuits and clocked dynamic logic that let a few engineers lay out roughly 2,300 transistors' worth of irregular control logic in the time available, using a self-aligned gate process Intel had adopted for memory but never applied to a chip with this much non-repeating logic.
This is a layout and circuit-design contribution, distinct from the instruction-set decisions Step 4 assumes as already given. The decoder's logical behavior was Mazor and Hoff's specification; the fact that it could be built, debugged, and yielded on schedule was Faggin's.
## 3. Why This Series Can Credit Specifically, Without Rewriting Steps 1 Through 10
Nothing in this attribution changes the architecture, instruction-set behavior, or decoder function this series already described. It answers a question those steps left open: who was responsible for each layer of decision. Hoff's proposal set the series' central thesis — behavior read from memory rather than fixed in silicon. Mazor's instruction-set work turned that thesis into a concrete, programmable machine. Faggin's silicon-gate implementation turned that machine into a device that could actually be fabricated, tested, and shipped. Crediting each separately is a correction of record, not a revision of the technical account.