MOSFET Scaling 1970s Adopt Self Aligned Polysilicon Gate

# MOSFET Scaling (1970s): Step 6 — Adopting the Self-Aligned Polysilicon Gate

The single process change that unlocked most of a decade of channel-length scaling. The self-aligned polysilicon gate process, developed in the late 1960s and adopted broadly across the industry through the early-to-mid 1970s, replaced the metal gate electrode with a heavily doped polycrystalline silicon electrode deposited and patterned before the source and drain are formed. Because the gate itself then serves as an implant/diffusion mask when the source and drain are driven in, channel length is set by a single lithography step rather than by the alignment of two independent ones. Step 6 covers the process flow and why it was close to a free lunch.

## 1. Process Sequence: Gate First, Diffusions Second

The sequence is: grow gate oxide; deposit polysilicon over the full wafer; pattern and etch the polysilicon to define the gate electrode in a single masking step; then introduce source/drain dopant (originally by diffusion, increasingly by ion implantation through the 1970s — see this series' step 10 and the dedicated ion-implantation series for the implant mechanics) using the already-patterned gate edge itself as the mask boundary. The result: the gap between source and drain — the electrical channel length — is fixed by the width of one already-defined feature, with zero added alignment tolerance.

## 2. Real Diagram: Self-Aligned vs. Non-Self-Aligned Channel Definition

Self-Aligned Gate: Why Channel Length No Longer Needs Alignment Margin the gate electrode itself masks the source/drain implant, fixing channel length in one step 1. Grow Gate Oxide thin thermal SiO2 over active area 2. Deposit + Pattern Polysilicon single mask defines gate width = channel length 3. Implant / Diffuse Source-Drain gate edge itself is the dopant mask boundary 4. Result: Channel Length Set Once no second-mask alignment tolerance added this single change removed alignment tolerance from the channel-length budget entirely

## 3. Why Polysilicon, Not Metal, Had to Be the Self-Aligned Electrode

The self-alignment trick only works if the gate material can survive the high-temperature step used to drive in or activate the source/drain dopant after the gate is already patterned — several hundred degrees Celsius for extended time, well above the melting or reflow point of aluminum. Polysilicon, already compatible with silicon processing and able to tolerate the same thermal budget as the substrate, was the material that made gate-first, diffusion-second sequencing possible. This is also why the gate material transition from metal to polysilicon during this era is inseparable from the channel-scaling story.

## 4. Secondary Benefits: Threshold Voltage and Overlap Capacitance

Beyond eliminating alignment margin, the self-aligned structure also minimized gate-to-source/drain overlap capacitance (parasitic overlap is now set by lateral dopant diffusion under the gate edge rather than by a deliberately oversized mask), which directly improved switching speed — a second, non-obvious payoff from the same structural change, and one more reason the industry converted to polysilicon gates quickly once the process was proven manufacturable.

## 5. Companion Diagram: Stage Sequence and Trend Summary

MOSFET Scaling (1970s): Step 6 stage sequence and schematic outcome trend for this step Process Sequence: G… 1 Real Diagram: Self-… 2 Why Polysilicon, No… 3 Secondary Benefits:… 4 sequence progression outcome trend (schematic) companion diagram: stage sequence and schematic trend for this step

## Adopting the Self-Aligned Polysilicon Gate's Place in the Process Lineage

This is step 6 of 20 in the MOSFET Scaling (1970s) series, tracing planar NMOS scaling from early 1970s field pressure through the fixed-voltage-scaling break that opens the adjacent HMOS (1978) series.

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