poly pitch metal pitch scaling
**Poly/Metal Pitch Scaling** addresses the **reduction of minimum repeating distances between transistor gates (contacted poly pitch, CPP) and metal interconnects (metal pitch, MP)** at each technology node — where pitch is the fundamental metric of density scaling, and the challenges of lithographic patterning, etching, deposition, and electrical performance converge to define each technology generation's capabilities.
**Pitch Scaling History**:
| Node | CPP (Contacted Poly Pitch) | Metal 1 Pitch | Key Enabler |
|------|---------------------------|---------------|-------------|
| 45nm | ~160nm | ~160nm | Immersion lithography |
| 22nm | ~90nm | ~80nm | Double patterning (SADP) |
| 14nm | ~70nm | ~52nm | FinFET + SADP |
| 7nm | ~54nm | ~36nm | EUV (select layers) |
| 5nm | ~48nm | ~28nm | EUV for most critical layers |
| 3nm | ~48nm | ~21nm | EUV + tighter design rules |
| **2nm** | ~45nm | ~18nm | GAA + High-NA EUV (future) |
**CPP Scaling Limiters**: CPP = gate length + 2×spacer width + 2×contact width. As each component shrinks: gate length cannot shrink below ~12nm (electrostatic control); spacer width cannot go below ~5nm (isolation, capacitance); contact width cannot shrink below ~10nm (contact resistance); and the total of minimum components = 12+10+20 = ~42nm minimum CPP. Further scaling requires: **buried power rails** (free up S/D contact space), **self-aligned contact** (relax overlay requirements), and **backside contacts** (remove some front-side routing).
**Metal Pitch Scaling Limiters**: Metal pitch = wire width + wire space. As pitch shrinks below ~30nm: **resistance** — wire width <15nm causes severe grain boundary and surface scattering (effective Cu resistivity 3-5× bulk); **capacitance** — narrow spacing increases plate capacitance, barely offset by low-k improvements; **reliability** — electromigration lifetime decreases with smaller cross-section (higher current density for same total current); and **patterning** — requires EUV (λ = 13.5nm) for single-exposure patterning below ~36nm pitch.
**Multi-Patterning at Tight Pitches**: When the target pitch is below the lithographic resolution limit, multiple exposures create the final pattern: **SADP** (Self-Aligned Double Patterning) — one litho/etch creates a mandrel, sidewall spacers become the final features at half the mandrel pitch; **SAQP** (Self-Aligned Quadruple Patterning) — two rounds of spacer formation, achieving 1/4 the original litho pitch; **LELE** (Litho-Etch-Litho-Etch) — two separate exposures each printing alternate features.
**Design Impact**: Tighter pitches constrain design rules: fewer routing tracks per standard cell, restricted via placement, unidirectional metal routing, and reduced options for signal routing. This pushes design complexity to the tool level — requiring advanced place-and-route algorithms and increasing cell area when routing congestion limits utilization.
**Poly and metal pitch scaling is the most tangible metric of semiconductor technology advancement — the numbers that ultimately determine transistor density and chip area, and whose relentless reduction driven by lithography, materials, and process innovation is the physical embodiment of Moore's Law continuing at the nanometer frontier.**