power delivery network design
**Power Delivery Network (PDN) Design** is the **comprehensive engineering of the electrical path that distributes supply voltage from external regulators through the package, bumps, and on-die metal grid to every transistor** — ensuring voltage remains within specifications (typically plus/minus 5% of nominal) under all static and dynamic load conditions.
**PDN Impedance Budget**
The fundamental approach is impedance-based: supply impedance must remain below Z_target = delta_V_allowed / I_max across all frequencies. For 0.75V supply with 5% tolerance and 100A peak current, Z_target = 37.5mV / 100A = 0.375 milliohm from DC to ~5 GHz.
| Frequency | Dominant Element | Concern |
|-----------|-----------------|----------|
| DC-1 kHz | VRM | Resistive IR drop |
| 1 kHz-10 MHz | Board/package decaps | VRM loop inductance |
| 10 MHz-500 MHz | Package + on-die decaps | Package inductance |
| 500 MHz-5 GHz | On-die decaps + grid C | Die-level resonance |
**On-Die Power Grid Design**: Uses mesh/grid topology on upper metal layers. Decisions include: **grid pitch** (tighter = lower IR drop but consumes routing resources), **metal layer allocation** (wider top metals for power, thinner lower for signal), **via arrays** between power layers (EM and IR drop), and **topology** (uniform mesh vs. non-uniform with wider straps near high-current blocks).
**Decoupling Capacitor Strategy**: On-die decaps are MOS capacitors in available whitespace. Effectiveness depends on: **capacitance density** (2-5 fF/um2), **ESR and ESL** (limit high-frequency effectiveness), **placement** (must be close to switching circuits), and **leakage** (thin-oxide decaps contribute gate leakage).
**Analysis and Signoff**: **Static IR drop** — DC simulation with worst-case current maps; **dynamic IR drop** — time-domain simulation capturing transient droops; **EM analysis** — current density verification; and **package co-simulation** — full VRM-through-die S-parameter modeling.
**Advanced Node**: Backside power delivery (BSPDN) routes power through wafer backside, freeing front-side metals for signals, reducing IR drop with shorter paths.
**PDN design is the foundation upon which all circuit performance rests — even brilliantly designed logic fails if power delivery cannot maintain supply integrity under real operating conditions.**