ir drop

**Power Grid Analysis (IR Drop / EM)** is the **simulation and optimization of power distribution network (PDN) — calculating voltage drops (IR: current × resistance) and electromigration (EM) in power/ground nets — ensuring supplies remain within 10% nominal across die and current density stays below material limits — critical for avoiding functional failure and improving reliability**. Power grid analysis is mandatory sign-off. **Static IR Drop Analysis** Static IR drop calculates voltage drop due to steady-state current distribution: V_drop = I × R (Ohm's law). Current is distributed from power pads (at die edge) through power straps (horizontal and vertical metal lines) to standard cells. Localized current density (A/µm²) varies: high-density logic draws more current, peripheral circuits less. Peak IR drop occurs at locations furthest from pads or with high current density. Static analysis assumes worst-case uniform current distribution; typical peak drop is 5-15% Vdd for designs without optimization. **Dynamic IR Drop and Transient Droop** During switching activity (clock edge, combinational logic transitions), current demand spikes can cause rapid voltage drop (transient droop). Dynamic IR drop is calculated via time-domain simulation: (1) activity pattern (switching frequency, current waveform) is simulated, (2) voltage response at every node calculated using RLC model of power grid, (3) transient voltage dip is quantified. Dynamic IR drop is worse than static: can reach 20-30% Vdd if not properly managed. Transient droop causes: (1) timing violations (devices slow down at low voltage), (2) latch-up risk (substrate injection), (3) signal integrity issues. **Current Density Map and EM Limits** Current density is current per unit width of conductor. Maximum allowable current density (J_max) depends on metal layer and wire width. Typical EM limits: (1) thick power straps (>1 µm width) — J_max ~2-5 MA/cm², (2) thin metal (0.1-0.5 µm) — J_max ~0.5-1 MA/cm². Exceeding J_max causes electromigration (EM) failure within 5-10 years of operation. Current density map overlays actual current distribution on metal grid, highlighting EM violations (red regions). **EMIR Signoff Tools** Electromagnetic IR (EMIR) analysis tools calculate IR drop and EM simultaneously: (1) Cadence Voltus — part of Cadence flow, industry-leading EMIR tool, (2) Mentor RedHawk — legacy but powerful, now Siemens, (3) Totem — newer entrant, focuses on fast analysis. EMIR input includes: (1) power grid layout (metal layers, straps, vias, pads), (2) current profile (activity file from simulation or estimation), (3) technology file (resistance/inductance per layer, EM limits). Output: voltage drop map, current density map, EM violations, recommended fixes. **Power Pad Placement Strategy** Power pads (C4 bumps, solder balls) are placed at die edges to connect package power distribution. Pad placement affects: (1) current path length (closer pads to logic reduce IR drop), (2) current distribution (uneven pad spacing creates local hot spots). Optimal pad placement uses clustering: pads are placed near power-hungry blocks (e.g., processor core, memory controllers). Pad spacing target is typically 5-10 mm for 300 mm die (uniform distribution). Pad orientation (rotated for symmetry) improves uniformity. **Power Straps and Hierarchy** Power distribution uses hierarchical approach: (1) primary straps (thick, low-resistance, on outermost metal layers like M9, M10) distribute current from pads across die, (2) secondary straps (medium thickness, intermediate layers) provide local distribution, (3) standard cell power rails (thin, lowest layers) connect to each standard cell. Strap width/spacing is tuned per layer: thick straps (2-10 µm wide, 20-50 µm spacing) in upper layers, thin straps (0.5-1 µm, 2-5 µm spacing) in lower layers. Strap pitch must be fine enough to avoid large IR drop between adjacent straps. **Decap Cell Insertion for Droop Reduction** On-chip decoupling capacitors (MOSCAPs or well-capacitors) charge during low-activity periods and discharge during switching peaks, buffering current demand and reducing transient droop. Decap insertion is performed after IR drop analysis: violations are identified, decaps are placed nearby to reduce voltage spike. Typical decap density is 1-5 fF per µm² of logic area (equivalent to 1-10 pF per 100 µm × 100 µm region). Decap placement is optimized via correlation: decaps are clustered where droop is worst. **Guard Ring and Substrate Coupling** Guard rings (p+ taps in n-substrate, n+ taps in p-substrate) provide multiple return paths for substrate current, reducing substrate resistance and noise coupling into analog/RF blocks. Guard rings also prevent latch-up: if parasitic pnp/npn structure is triggered (rare), guard ring provides low-resistance path to ground before snapback occurs. Guard ring spacing is typically 100-300 µm (fine spacing in sensitive areas). **Power Grid Optimization Flow** Optimization iterates: (1) initial grid design (based on rules-of-thumb and routing congestion), (2) IR/EM analysis (identify violations), (3) fix violations (add straps, increase width, add decaps, move pads), (4) repeat until all margins met. Typical optimization requires 3-5 iterations. Margins target: (1) max IR drop <8% Vdd (leaving margin for noise, variation), (2) peak dynamic droop <10% Vdd, (3) all metal at <80% J_max (safety margin for aging). **Summary** Power grid analysis and optimization are essential for reliable, high-performance design. Continued advances in EM modeling, dynamic simulation, and automatic optimization drive improved margins and chip reliability.