semiconductor memory types
**Semiconductor Memory Technologies** are the **diverse family of storage devices fabricated on silicon, ranging from ultra-fast SRAM registers to high-density NAND flash** — each occupying a distinct position in the speed-capacity-cost hierarchy that defines computer architecture, where the choice of memory technology for each level of the hierarchy is driven by the fundamental physics tradeoffs between access speed, density, power, and data retention.
**Memory Hierarchy**
| Level | Technology | Size | Latency | $/GB |
|-------|-----------|------|---------|------|
| Registers | Flip-flops | 1-10 KB | ~0.3 ns | — |
| L1 Cache | SRAM | 32-128 KB | ~1 ns | ~$10,000 |
| L2 Cache | SRAM | 256KB-2MB | ~3-5 ns | ~$5,000 |
| L3 Cache | SRAM | 4-256 MB | ~10-20 ns | ~$1,000 |
| Main Memory | DRAM | 4-512 GB | ~50-100 ns | ~$3-5 |
| SSD Storage | NAND Flash | 256GB-30TB | ~20-100 μs | ~$0.05-0.10 |
| HDD Storage | Magnetic | 1-20 TB | ~5-10 ms | ~$0.01-0.02 |
**SRAM (Static RAM)**
- **Cell**: 6 transistors (6T) per bit — two cross-coupled inverters + two access transistors.
- **Pros**: Fastest, no refresh needed, fully CMOS-compatible.
- **Cons**: Largest cell (100-200 F²), highest cost per bit.
- **Use**: CPU caches, register files, embedded memory.
- **Advanced node**: Bitcell scaling slowing down — SRAM area reduction lags logic scaling.
**DRAM (Dynamic RAM)**
- **Cell**: 1 transistor + 1 capacitor (1T1C) per bit.
- **Data storage**: Charge on capacitor — must be refreshed every 64 ms (charge leaks).
- **Pros**: 4-6x denser than SRAM, much cheaper per bit.
- **Cons**: Slower, requires refresh (power overhead), separate manufacturing.
- **Types**: DDR5, LPDDR5 (mobile), HBM3 (GPU/AI — stacked DRAM).
**NAND Flash**
- **Cell**: Floating gate or charge trap transistor.
- **Data storage**: Electrons trapped in floating gate → shifts Vt → encodes bits.
- **Multi-level**: SLC (1 bit/cell), MLC (2), TLC (3), QLC (4), PLC (5 — emerging).
- **3D NAND**: Stack 100-300+ layers vertically → massive density increase.
- **Endurance**: SLC: 100K P/E cycles, TLC: 1-3K cycles, QLC: 500-1K cycles.
**Emerging Memories**
| Technology | Principle | Status | Target |
|-----------|----------|--------|--------|
| MRAM (STT/SOT) | Magnetic tunnel junction | Production | IoT, embedded NVM |
| ReRAM/RRAM | Resistive switching | Limited production | Embedded, neuromorphic |
| PCM | Phase change (crystalline/amorphous) | Production (Intel Optane discontinued) | Storage class memory |
| FeRAM | Ferroelectric polarization | Niche production | Low-power embedded |
Semiconductor memory technologies are **the complementary partners to logic in every computing system** — the performance of any application is ultimately limited by how fast data can be accessed, making memory technology advancement as critical as processor scaling for continued computing progress.