Silicon Grown Junction 1954 Form First Junction
# Form First Junction: Metallurgical Crossover and Silicon's 1.12 eV Built-In Potential
Prior steps focused on high-temperature liquid kinetics and dopant dissolution; the instant the freezing interface passes the metallurgical crossover where solid gallium acceptor concentration overtakes antimony donors, the growth boundary ceases to be merely a chemical artifact and becomes an electrostatic p-n junction. Inside the continuous diamond-cubic crystal lattice, mobile electrons and holes diffuse across the newly solidified boundary, leaving behind uncompensated ionized donor and acceptor charges that erect a space-charge depletion region and a powerful internal electric field. While the mechanical mechanism mirrors the 1951 germanium process, the physical behavior inside silicon is fundamentally transformed: silicon’s wide $1.12\ \text{eV}$ bandgap raises the built-in potential to $V_{bi} \approx 0.72\ \text{V}$ (compared to germanium’s $\sim 0.38\ \text{V}$) and suppresses intrinsic thermal carrier generation ($n_i$) by six orders of magnitude. This electrostatic boundary is the physical reason Gordon Teal’s 1954 transistor could withstand temperatures that destroyed germanium devices.
## 1. Silicon's 1.12 eV Bandgap and the Elevated Built-In Potential
The electrostatics of the collector-base junction are governed by the disparity between the dopant concentrations and the intrinsic carrier density of the semiconductor:
1. The Doping Levels Across the Boundary:
* Collector Side (n-type): Donor concentration $N_D \approx 1.3 \times 10^{15}\ \text{atoms/cm}^3$ (antimony-doped).
* Base Side (p-type): Acceptor concentration $N_A \approx 1.0 \times 10^{17}\ \text{atoms/cm}^3$ (gallium-doped).
2. Comparing Silicon and Germanium Built-In Potentials:
In germanium ($E_g \approx 0.66\ \text{eV}$), intrinsic carrier density at room temperature is relatively high ($n_i \approx 2.4 \times 10^{13}\ \text{cm}^{-3}$), yielding a modest built-in barrier of $V_{bi} \approx 0.38\ \text{V}$. In silicon, the wider $1.12\ \text{eV}$ bandgap suppresses intrinsic carriers to $n_i \approx 1.5 \times 10^{10}\ \text{cm}^{-3}$. Because $n_i^2$ is smaller by a factor of $2.5 \times 10^6$, the electrostatic barrier rises to:
3. The Physics of High-Temperature Survival:
Reverse saturation leakage current density $J_0$ depends directly on $n_i^2$:
At 100°C ($373\ \text{K}$), germanium’s intrinsic carrier density surges past $10^{15}\ \text{cm}^{-3}$, matching the collector background doping and causing runaway thermal leakage that destroys transistor amplification. In silicon at 100°C, $n_i$ remains below $10^{12}\ \text{cm}^{-3}$, preserving high junction impedance, sub-microampere leakage, and stable transistor action up to 150°C.
## 2. Real Diagram: Space Charge, Depletion Region, and Built-In Field
## 3. Asymmetric Depletion and Punch-Through Margin
The physical width of the depletion layer is an automatic consequence of Poisson's equation across the doping step:
1. One-Sided Step Junction Behavior:
Because the p-type base acceptor concentration ($N_A \approx 1.0 \times 10^{17}\ \text{cm}^{-3}$) is nearly two orders of magnitude higher than the collector donor concentration ($N_D \approx 1.3 \times 10^{15}\ \text{cm}^{-3}$), the junction behaves electrostatically as a one-sided $p^+$-$n$ step junction.
2. Depletion Width Distribution:
With silicon's relative permittivity $\varepsilon_r \approx 11.7$ ($\varepsilon_s = 1.036 \times 10^{-12}\ \text{F/cm}$), the total equilibrium depletion width is:
By Gauss's law, total exposed donor charge equals exposed acceptor charge ($q N_D x_n = q N_A x_p$). Consequently, the depletion zone extends $x_n \approx 0.84\ \mu\text{m}$ into the collector, but only $x_p = x_n (N_D / N_A) \approx 0.011\ \mu\text{m}$ ($11\ \text{nanometers}$) into the base.
3. Punch-Through Immunity:
In upcoming Step 16, the base will be grown to a scheduled physical width of $W_B \sim 25\ \mu\text{m}$. Because base-side depletion penetration is a negligible $11\ \text{nm}$ at zero bias and expands to only $\sim 0.06\ \mu\text{m}$ under a reverse collector bias of $30\ \text{V}$, the collector depletion region is physically incapable of punching through to the emitter junction. This ensures that the transistor maintains high collector voltage ratings without premature short-circuit breakdown.
## Form First Junction's Place in the Process Lineage
Forming the first junction is step fifteen of this project's 1954 silicon grown-junction transistor series — following the incorporation and mixing of the acceptor dopant, and preceding the growth of the thin p-type base. It marks the transition where high-temperature crystal growth produces its first electrically functional semiconductor structure: a collector-base p-n junction with a $0.72\ \text{V}$ built-in potential and nano-ampere leakage currents enabled by silicon's $1.12\ \text{eV}$ bandgap. Step sixteen, grow thin p-type base, pulls crystal at steady velocity for a timed interval to set the physical thickness of the transistor's active control layer.