Silicon Grown Junction 1954 Form Second Junction

# Form Second Junction: Closing the Monolithic N-P-N Silicon Structure

Until this moment, the collector-base junction formed in Step 15 existed as an isolated electrostatic boundary; the instant the freezing silicon front passes the second metallurgical crossover where solid antimony donor concentration overtakes gallium acceptors, that isolation ends and a fully coupled three-layer bipolar transistor emerges. The thin p-type base is now flanked on either side by opposite-polarity semiconductor regions, bounded by two distinct space-charge depletion layers that terminate electric fields within a single continuous crystal lattice. Because the newly created emitter is heavily doped ( $N_D^+ \approx 2.0 \times 10^{18}\ \text{cm}^{-3}$ ), its built-in potential against the base reaches $V_{bi} \approx 0.89\ \text{V}$ —over $0.4\ \text{V}$ higher than its germanium counterpart. This step establishes the complete monolithic n-p-n sandwich, coupling the emitter and collector electrostatics across the $25\ \mu\text{m}$ base without risking punch-through breakdown.

## 1. Coupling the Sandwich and the High-Barrier Emitter-Base Electrostatics

V_{bi,\text{EB}} = \frac{kT}{q} \ln\!\left(\frac{N_A \, N_D^+}{n_i^2}\right) \approx 0.89\ \text{V} \quad \text{vs.} \quad V_{bi,\text{EB}}(\text{Ge}) \approx 0.45\ \text{V}

The physical completion of the second junction transforms three separate crystal regions into an integrated electrical entity:
1. The Three-Layer Doping Hierarchy:
* Collector (n-type): $N_D \approx 1.3 \times 10^{15}\ \text{atoms/cm}^3$ (lightly doped for high breakdown voltage).
* Base (p-type): $N_A \approx 1.0 \times 10^{17}\ \text{atoms/cm}^3$ (moderately doped, $W_B \approx 25\ \mu\text{m}$ ).
* Emitter ( $$n^+$$ -type): $N_D^+ \approx 2.0 \times 10^{18}\ \text{atoms/cm}^3$ (heavily doped for high injection efficiency).
2. The 0.89 V Emitter Barrier in Silicon:
In germanium, the narrower bandgap ( $0.66\ \text{eV}$ ) limited the emitter-base built-in barrier to roughly $0.45\ \text{V}$ . In silicon, the $1.12\ \text{eV}$ bandgap and depressed intrinsic carrier concentration ( $n_i \approx 1.5 \times 10^{10}\ \text{cm}^{-3}$ ) raise the built-in potential across the emitter-base junction to:

V_{bi,\text{EB}} \approx 0.0259 \, \ln\!\left(\frac{1.0 \times 10^{17} \times 2.0 \times 10^{18}}{2.25 \times 10^{20}}\right) \approx 0.89\ \text{V}

3. Turn-On Voltage Characteristics:
Because the built-in electrostatic barrier is nearly $0.9\ \text{V}$ , forward conduction in the emitter junction requires applying a forward bias of $V_{BE} \approx 0.65\text{ to }0.70\ \text{V}$ (compared to only $\approx 0.2\text{ to }0.3\ \text{V}$ in germanium). This elevated turn-on threshold makes the silicon transistor vastly more immune to false triggering from thermal noise or ambient leakage currents at elevated operating temperatures.

## 2. Real Diagram: Dual Depletion Regions and the Coupled N-P-N System

## 3. The Punch-Through Condition and Neutral Base Integrity

W_B > x_{p,\text{CB}}(V_{\text{CB}}) + x_{p,\text{EB}}(V_{\text{EB}}) \quad \text{and} \quad W_{B,\text{neutral}} = W_B - \Delta W_{\text{dep}}

With two junctions bounding the base, the device operates safely only as long as a field-free neutral base region separates the two space-charge layers:
1. The Nature of Punch-Through Breakdown:
If the collector-base depletion layer expands across the base under high collector voltage and touches the emitter depletion layer, the potential barrier at the emitter collapses. Electrons flood from the emitter directly into the collector without base control, causing immediate circuit failure.
2. Depletion Penetration Calculations:
* Emitter-Base Side: Because the emitter is heavily doped ( $N_D^+ \approx 2 \times 10^{18}\ \text{cm}^{-3}$ ), the E-B depletion width is only $0.11\ \mu\text{m}$ . Penetration into the base is $x_{p,\text{EB}} \approx 0.10\ \mu\text{m}$ at zero bias, and shrinks to $< 0.05\ \mu\text{m}$ under forward active bias ( $V_{BE} \approx 0.7\ \text{V}$ ).
* Collector-Base Side: Under an aggressive reverse operating bias of $V_{CB} = 25\ \text{V}$ , the total C-B depletion layer widens to $\sim 5.0\ \mu\text{m}$ . However, because the base doping is almost $100\times$ higher than the collector doping, the penetration into the base is constrained by Gauss's law to:

x_{p,\text{CB}}(25\text{V}) \approx \frac{N_{D,\text{coll}}}{N_A} \times 5.0\ \mu\text{m} \approx \frac{1.3 \times 10^{15}}{1.0 \times 10^{17}} \times 5.0\ \mu\text{m} \approx 0.065\ \mu\text{m}

3. Total Base Consumption Under Bias:
Combined depletion penetration from both sides under full operating bias is less than $0.15\ \mu\text{m}$ . Subtracting this from the physical metallurgical base thickness $W_B \approx 25.0\ \mu\text{m}$ leaves an active neutral base width of $W_{B,\text{neutral}} \approx 24.85\ \mu\text{m}$ —retaining over $99\%$ of its field-free diffusion zone. This guarantees high collector breakdown voltage ( $V_{\text{CBO}} > 40\ \text{V}$ ) with complete punch-through immunity.

## Form Second Junction's Place in the Process Lineage

Forming the second junction is step eighteen of this project's 1954 silicon grown-junction transistor series — immediately following the introduction of the donor dopant pellet, and preceding the growth of the second n-type region. It is the architectural culmination of the junction-pulling phase, closing the n-p-n sandwich into an integrated three-terminal semiconductor device with a $0.89\ \text{V}$ emitter barrier and robust punch-through immunity. Step nineteen, grow second n-type region, pulls the final crystal section to provide the physical bulk and lead-attachment pad for the transistor emitter.

Silicon Grown Junction 1954 Form Second Junction

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