source drain stress engineering

**Source Drain Stress Engineering** is the **device performance tuning method that introduces local stressors near source and drain regions**. **What It Covers** - **Core concept**: uses material choice and geometry to boost carrier mobility. - **Engineering focus**: balances NMOS tensile and PMOS compressive targets. - **Operational impact**: improves drive current without major area penalty. - **Primary risk**: stress variability can increase device mismatch. **Implementation Checklist** - Define measurable targets for performance, yield, reliability, and cost before integration. - Instrument the flow with inline metrology or runtime telemetry so drift is detected early. - Use split lots or controlled experiments to validate process windows before volume deployment. - Feed learning back into design rules, runbooks, and qualification criteria. **Common Tradeoffs** | Priority | Upside | Cost | |--------|--------|------| | Performance | Higher throughput or lower latency | More integration complexity | | Yield | Better defect tolerance and stability | Extra margin or additional cycle time | | Cost | Lower total ownership cost at scale | Slower peak optimization in early phases | Source Drain Stress Engineering is **a practical lever for predictable scaling** because teams can convert this topic into clear controls, signoff gates, and production KPIs.