strained

**Strained Silicon and Epitaxial Process Engineering** is **intentional introduction of mechanical stress into silicon channels to enhance carrier mobility — enabling higher performance through lattice-mismatched heteroepitaxial growth or post-growth stress engineering**. Strained silicon improves transistor performance by enhancing carrier mobility. Mechanical stress modifies the electronic band structure, changing effective mass and scattering rates. Tensile stress in NMOS channels reduces electron effective mass, increasing electron mobility (>50% improvement). Compressive stress in PMOS channels modifies band structure to increase hole mobility (~70% improvement). Performance improvements at constant power enable faster circuits or lower power at fixed performance. Strain engineering provides mobility gains equivalent to geometric scaling at reduced cost. Epitaxial growth enables strained silicon layers. Depositing Si:Ge (silicon-germanium) alloy on silicon substrate creates lattice mismatch — Ge has larger lattice constant than Si. Growing SiGe on Si causes tensile stress in the SiGe due to constraint by underlying Si. A thin Si cap layer on SiGe experiences tensile stress. For NMOS, tensile-stressed Si channels are grown on SiGe. For PMOS, compressive stress is obtained through other techniques. Process involves careful epitaxial growth control — growth rate, temperature, precursor chemistry affect final Ge concentration and quality. Ge concentration determines lattice mismatch and resulting stress. Higher Ge percentage increases mismatch but risks defect formation (misfit dislocations). Typical Ge concentrations are 15-30%. Post-growth annealing can modify stress but risks Ge segregation or defect generation. Stressor layers (SLT) are deposited dielectric materials (nitride) that constrain underlying silicon during deposition. Nitride deposition at elevated temperature creates intrinsic compressive stress in the film. Upon cooling, differential thermal expansion between nitride and underlying silicon creates additional stress. SLT stress is significant — tuning SLT thickness and composition provides process handles. NMOS benefits from tensile-stressed SLT (pulling source/drain contact regions). PMOS benefits from compressive-stressed SLT. SLT placement and patterning enable selective stress application. Different stress can be applied to different transistor types. Contact etch stop layers (CESL) and other contact structures can be engineered to apply stress. Three-dimensional strain in FinFETs and nanosheet transistors requires sophisticated strain analysis. Stress is non-uniform and depends on fin/wire geometry and surrounding material. Modeling and optimization are essential. Strain compatibility between different device types on the same chip requires careful design. Process-induced stress variations limit strain benefits. Scaling strain engineering to sub-7nm nodes becomes increasingly difficult. Extreme requirements for precision and uniformity challenge manufacturing. **Strained silicon and epitaxial engineering provide substantial mobility enhancements enabling continued performance scaling with reduced geometric aggressiveness.**