through-interposer via
**Through-Interposer Via (TIV)** is a **vertical electrical connection that passes completely through a silicon or organic interposer** — connecting the chiplets mounted on the top surface to the package substrate on the bottom surface, functioning as the critical vertical pathway that enables 2.5D packaging by routing power, ground, and signals between the fine-pitch chiplet bumps above and the coarser-pitch package balls below.
**What Is a TIV?**
- **Definition**: A conductive via (typically copper-filled) that extends through the full thickness of an interposer substrate — in silicon interposers, TIVs are essentially TSVs (through-silicon vias) fabricated in the interposer die; in organic interposers, TIVs are plated through-holes or laser-drilled microvias that span the full substrate thickness.
- **TSV in Interposer Context**: When TSVs are fabricated in an interposer (rather than in an active die), they are sometimes called TIVs to distinguish them from TSVs in functional chips — the fabrication process is similar (DRIE etch, oxide liner, copper fill) but the interposer TSVs are typically larger diameter and lower aspect ratio.
- **Pitch Translation**: TIVs perform a critical pitch translation function — converting the fine bump pitch on top (40-55 μm for chiplet micro-bumps) to the coarser pitch on the bottom (100-150 μm for C4 bumps to the package substrate).
- **Density**: A typical silicon interposer for an AI GPU contains 10,000-100,000+ TIVs — carrying power, ground, and signal connections for multiple chiplets and HBM stacks.
**Why TIVs Matter**
- **2.5D Enabler**: Without TIVs, there is no vertical path through the interposer — chiplets on top cannot connect to the package substrate below, making 2.5D integration impossible.
- **Power Delivery**: A significant fraction of TIVs (often 50-70%) carry power and ground — the GPU and HBM stacks on a CoWoS interposer can draw 500-1000W total, requiring thousands of low-resistance power TIVs.
- **Signal Integrity**: TIV parasitics (resistance, capacitance, inductance) affect signal quality for high-speed die-to-die and die-to-package connections — TIV design must minimize these parasitics while maintaining mechanical reliability.
- **Thermal Path**: TIVs also serve as thermal conduits — copper-filled vias conduct heat from the chiplets through the interposer to the package substrate and heat sink below.
**TIV Fabrication Process**
- **Via Etching**: Deep reactive ion etching (DRIE) using the Bosch process creates high-aspect-ratio holes in silicon — typical TIV dimensions are 5-10 μm diameter, 50-100 μm deep (aspect ratio 5:1 to 10:1).
- **Insulation**: SiO₂ or SiN liner deposited by CVD to electrically isolate the copper via from the silicon substrate — liner thickness 100-500 nm.
- **Barrier/Seed**: TaN/Ta barrier layer and Cu seed layer deposited by PVD — prevents copper diffusion into silicon and provides the nucleation layer for electroplating.
- **Copper Fill**: Bottom-up electroplating fills the via with copper — requires specialized plating chemistry with suppressor/accelerator additives to achieve void-free fill.
- **CMP**: Chemical-mechanical planarization removes excess copper from the wafer surface — creating a flat surface for subsequent metal routing layers.
| TIV Parameter | Silicon Interposer | Organic Interposer |
|--------------|-------------------|-------------------|
| Via Diameter | 5-10 μm | 25-75 μm |
| Via Depth | 50-100 μm | 100-400 μm |
| Aspect Ratio | 5:1 - 10:1 | 2:1 - 5:1 |
| Via Pitch | 40-100 μm | 100-300 μm |
| Fill Material | Copper (electroplated) | Copper (plated) |
| Formation | DRIE | Laser drill |
| Resistance | < 50 mΩ | < 100 mΩ |
| Density | 10K-100K+ per interposer | 1K-10K per interposer |
**TIVs are the essential vertical interconnects that make 2.5D packaging work** — providing the through-interposer pathways for power delivery, signal routing, and thermal conduction that connect chiplets to the package substrate, with TIV density, resistance, and reliability directly determining the performance and power efficiency of multi-die AI GPU and HPC packages.