wafer level chip scale packaging
**Wafer-Level Chip-Scale Packaging (WLCSP)** is **a packaging technology where all interconnect and protection layers are fabricated directly on the wafer before singulation, producing a finished package with the same footprint as the die itself—no substrate, no wire bonds, and no molding compound**.
**WLCSP Architecture:**
- **Package Size**: true chip-scale—package dimensions equal die dimensions (≤1.2x die size per JEDEC definition), typically 0.3-5 mm per side
- **Bump Pitch**: solder ball pitch ranges from 0.3-0.5 mm for standard WLCSP; fine-pitch WLCSP achieves 0.35 mm pitch
- **Redistribution Layer (RDL)**: 1-2 metal layers (Cu, 5-10 µm thick) redistribute peripheral I/O pads to area-array solder ball pattern on die face
- **Ball Count**: typically 4-200 solder balls; limited by die size and minimum bump pitch
- **Passivation Stack**: polyimide or PBO (polybenzoxazole) dielectric layers (5-15 µm) provide mechanical protection and stress buffering
**WLCSP Fabrication Process:**
- **Passivation Deposition**: PECVD SiN/SiO₂ passivation followed by spin-coated polymer (PI or PBO) at 5-10 µm thickness
- **RDL Formation**: sputter Ti/Cu seed layer, pattern with photoresist, electroplate Cu traces (5-8 µm), strip resist and etch seed
- **Under-Bump Metallurgy (UBM)**: sputter or plate Ni (3-5 µm) / Au (0.05 µm) or Cu/Ni stack to provide solderable surface and diffusion barrier
- **Solder Ball Attach**: place eutectic SnAg (96.5Sn3.5Ag) solder balls (150-300 µm diameter) by stencil printing or ball drop, reflow at 250°C peak
- **Wafer-Level Test**: probe testing at wafer level before singulation; known-good-die (KGD) marking
- **Dicing**: blade or laser singulation into individual WLCSP packages
**Reliability Considerations:**
- **Board-Level Reliability**: critical concern—no underfill in standard WLCSP means solder joints absorb all CTE mismatch stress between die (Si: 2.6 ppm/°C) and PCB (16-18 ppm/°C)
- **Thermal Cycling Life**: typical specification 500-1000 cycles (−40 to +125°C); corner balls experience highest strain and fail first
- **Drop Test Performance**: WLCSP vulnerable to drop shock—solder joint fracture at UBM interface; JEDEC JESD22-B111 qualification requires 30+ drops from 150 cm
- **Polymer Stress Buffer**: thick PBO/PI layers (>8 µm) absorb stress and improve thermal cycling life by 2-3x compared to thin passivation only
- **Solder Joint Fatigue**: Coffin-Manson model predicts fatigue life from plastic strain range; corner ball DNP (distance from neutral point) determines strain magnitude
**Fan-Out Wafer-Level Packaging (FOWLP):**
- **Concept**: die embedded in reconstituted molded wafer with RDL extending beyond die edge—decouples package I/O from die size
- **eWLB (TSMC InFO)**: embedded wafer-level ball grid array; enables RDL fan-out to >500 I/Os for application processors
- **RDL Layers**: 2-4 Cu RDL layers with minimum L/S of 2/2 µm for high-density fan-out
- **Applications**: Apple A-series processors, Qualcomm Snapdragon, RF front-end modules
**WLCSP Applications:**
- **Target Devices**: analog ICs, PMICs, RF components, sensors, small microcontrollers—devices with moderate I/O count (<200 pins)
- **Advantages**: smallest form factor, lowest inductance (short interconnect path), excellent thermal performance (direct die-to-board attachment), lowest cost for small die
**WLCSP and its fan-out derivatives represent the most area-efficient packaging solutions in the semiconductor industry, enabling the compact form factors demanded by mobile, wearable, and IoT devices while pushing the boundaries of board-level reliability through advanced stress engineering and solder joint optimization.**