what are chiplets
**Chiplets and 2.5D/3D integration are the packaging-level answer to a problem lithography itself can no longer solve alone: building one giant monolithic chip has stopped being the most practical way to keep AI silicon scaling.** Every process step covered earlier in this series' fab chain — lithography, plasma etch, CVD, ion implantation, CMP — happens on a single continuous piece of silicon, and a design's reticle limit caps how large that single piece can physically be in one exposure. Cramming more capability onto a chip used to mean simply making that one die bigger or packing transistors tighter; chiplets take a different approach entirely, splitting what would have been one enormous die into several smaller dies — chiplets — manufactured separately, often on different process nodes, and then reassembled into a single package that behaves like one chip.
**The reason this works at all is that not every part of a modern AI chip benefits equally from the most expensive, most advanced process node.** A dense compute core benefits enormously from a cutting-edge node's smaller, faster transistors — recall the FinFET-to-GAA discussion, where tighter gate control directly improves both speed and power efficiency. But I/O circuits, memory controllers, and other supporting logic often perform just as well on an older, cheaper, higher-yielding node. Splitting a design into chiplets lets each piece be built on whichever node actually benefits it, then combined in packaging — the compute chiplet on the newest, priciest node; everything else on nodes that are proven, cheaper, and produce fewer defective dies per wafer.
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**2.5D and 3D integration are two different ways of physically arranging those chiplets, and the earlier HBM/packaging discussion already introduced the 3D half of this story.** In 2.5D integration, chiplets sit side by side on top of a shared substrate called an interposer — often itself made of silicon, densely wired to carry signals between the chiplets sitting on it — which keeps the chiplets close enough together that communication between them stays fast, without needing them to be physically stacked. 3D integration goes further, stacking dies directly on top of one another and connecting the layers with through-silicon vias (TSVs) — the same vertical-connection concept behind HBM's stacked memory layers, covered earlier in the wafer test and packaging entry. Stacking shortens the physical distance signals travel even further than 2.5D, at the cost of harder thermal management, since heat generated deep in a stack has to travel further to escape.
| Approach | Physical Arrangement | Main Benefit | Main Challenge |
|---|---|---|---|
| Monolithic Die | Entire design on one continuous die | Simplest design, no packaging complexity | Capped by reticle limit; one defect can void the whole die |
| 2.5D (Interposer) | Chiplets placed side by side on a shared interposer | Mix process nodes; smaller dies improve yield | Interposer adds cost and a longer signal path than stacking |
| 3D (TSV Stacking) | Chiplets stacked vertically, connected by TSVs | Shortest possible interconnect distance | Harder heat removal from buried layers |
```flowchart
st=>start: Design split into functional blocks — compute, I/O, memory controllers
assign=>operation: Each block assigned to whichever process node best fits its needs
fab=>operation: Each chiplet fabricated separately through the standard fab process chain
test=>operation: Each chiplet tested individually before assembly (catches defects early, protects yield)
package=>operation: Good chiplets combined via 2.5D interposer or 3D TSV stacking
verify=>operation: Assembled package tested as a single unit before shipping
pass=>end: Finished chip behaves as one device, built from several separately-optimized dies
st->assign->fab->test->package->verify->pass
```
**This directly explains why chiplets have become central to modern AI accelerator strategy, and it ties every earlier packaging and yield discussion together.** Testing each chiplet individually before assembly — exactly the wafer-probe-test step covered in the wafer test and packaging entry — means a defect only wastes one small chiplet instead of an entire enormous monolithic die, meaningfully improving overall yield and cost as designs get larger and more complex. And because compute and memory can be built as separate optimized chiplets and then stacked or placed side by side, the same fundamental memory-bandwidth story running through this whole series — decode needing fast access to weights and the KV cache — gets a direct hardware answer: put the memory as physically close to the compute as 2.5D or 3D integration allows, shortening exactly the data path that so much of the inference-side discussion has been about widening and speeding up.