CFS Transistor Devices University

P-N Junction Physics — Built-In Potential ($V_{bi}$) and Space Charge

Pure silicon is an insulator until we add specific impurity atoms. When we dope silicon with phosphorus (Group V), it gains free conduction electrons, creating n-type silicon. When we dope it with boron (Group III), it lacks valence electrons, creating mobile positive holes in p-type silicon.

When an n-type and p-type region touch, electrons diffuse across the border to fill nearby holes. This leaves behind uncovered, positively charged donor ions ($N_D^+$) on the n-side and negatively charged acceptor ions ($N_A^-$) on the p-side, forming a neutral insulating barrier called the Depletion Region.

• Built-In Potential ($V_{bi}$): The electrostatic barrier stopping further spontaneous carrier diffusion.
• Space-Charge Layer: A region stripped of mobile carriers containing fixed ionized atomic lattice cores.

The Field-Effect Principle — Voltage-Controlled Conduction

Early electronics used glass vacuum tubes that required boiling-hot tungsten filaments consuming watts of power. In 1925, Julius Lilienfeld patented the concept of the Field-Effect Transistor (FET): controlling the electrical conductivity of a solid material using an external transverse electric field.

By placing a metal electrode over an insulating dielectric layer (like glass or silicon dioxide), applying a positive voltage to the gate terminal creates a vertical electric field $\mathcal{E}$. This field penetrates the semiconductor substrate, repelling mobile holes away from the surface and attracting negative electrons to form a conductive skin.

• High Input Impedance: Because the gate is separated by an insulator, almost zero steady current flows ($R_{\text{in}} > 10^{14}\,\Omega$).
• Pure Voltage Control: The device is controlled by electrostatic potential rather than driving input current.

Depletion Width Modulation ($W_{\text{dep}}$) Under Reverse Bias

When you apply a reverse bias voltage $V_R$ across a P-N junction (negative to p-side, positive to n-side), the external battery pulls mobile electrons and holes even further away from the interface. This expands the depletion layer width $W_{\text{dep}}$, creating a wider insulating gap that blocks current flow.

Because charge is stored across a variable insulating gap, the P-N junction acts as a voltage-variable capacitor (a varactor). The depletion width is governed directly by Poisson\x27s equation relating spatial charge density $\rho(x)$ to electric potential curvature:

• Wider Barrier: Higher reverse voltage increases $W_{\text{dep}}$ proportionally to $\sqrt{V_{bi} + V_R}$.
• Junction Capacitance: Scales inversely with width, $C_j = \epsilon_s A / W_{\text{dep}}$.

Accumulation, Depletion, and Strong Inversion ($\phi_s = 2\phi_B$)

The core of modern digital electronics is the MOS Capacitor (Metal-Oxide-Semiconductor). When we vary the gate voltage $V_G$ on a p-type substrate, energy bands bend upward or downward at the silicon surface, establishing three operational regimes:

• Accumulation ($V_G < V_{FB}$): Negative voltage pulls majority holes to the surface, forming a dense positive hole layer.
• Depletion ($V_{FB} < V_G < V_{th}$): Moderate positive voltage repels holes, leaving fixed ionized acceptor atoms ($N_A^-$).
• Strong Inversion ($V_G \ge V_{th}$): High positive voltage bends the conduction band $E_c$ below the Fermi level $E_F$, pulling a dense layer of minority electrons to create an n-type inversion channel!

Threshold Voltage ($V_{th}$) Derivation & Fixed Oxide Charges

The Threshold Voltage ($V_{th}$) is the gate voltage required to turn the transistor from an insulating barrier into a conductive channel. Mathematically, the gate voltage must overcome three physical barrier terms:

1. The flat-band voltage $V_{FB}$ to cancel out metal-semiconductor workfunction difference ($\Phi_{ms}$) and interface oxide charge ($Q_{ox}$).
2. The surface potential required for strong inversion ($2\phi_B$).
3. The voltage dropped across the oxide dielectric to support the depletion layer charge ($Q_{\text{dep}} / C_{ox}$).

• Bulk Body Effect: Reverse body bias $V_{SB}$ increases depletion charge, raising $V_{th}$ by $\gamma (\sqrt{2\phi_B + V_{SB}} - \sqrt{2\phi_B})$.

Gate Dielectric Capacitance ($C_{ox}$) & Equivalent Oxide Thickness (EOT)

To maximize transistor switching speed and drive current, the gate capacitance per unit area $C_{ox} = \epsilon_{ox} / t_{ox}$ must be as large as possible. Historically, foundries scaled silicon dioxide ($\text{SiO}_2$) down to $1.2\text{ nm}$ — just 5 silicon atoms thick!

At $1.2\text{ nm}$, quantum mechanical electron tunneling caused catastrophic gate leakage. In 2007, the industry introduced High-$\kappa$ Metal Gate (HKMG) using Hafnium Oxide ($\text{HfO}_2, \kappa \approx 22$) instead of $\text{SiO}_2 (\kappa = 3.9)$. This allows a physically thicker film ($3\text{ nm}$) that blocks tunneling while providing the capacitance of a $0.8\text{ nm}$ oxide!

• Equivalent Oxide Thickness (EOT): $\text{EOT} = t_{\text{high-}\kappa} \left(\frac{\kappa_{\text{SiO}_2}}{\kappa_{\text{high-}\kappa}}\right)$.
• Quantum Tunneling: Suppressed exponentially with physical barrier thickness $t_{\text{phys}}$.

Gradual Channel Approximation & Long-Channel Current ($I_D$)

The classical Drift-Diffusion model assumes carrier velocity is proportional to lateral electric field, $v_d = \mu_{\text{eff}} \mathcal{E}_x$. Applying the Gradual Channel Approximation ($|\partial \mathcal{E}_x / \partial x| \ll |\partial \mathcal{E}_y / \partial y|$) across channel length $L$ and width $W$, the inversion charge density is $Q_{\text{inv}}(x) = -C_{ox}[V_{GS} - V_{th} - V(x)]$.

Integrating $I_D = -W v_d Q_{\text{inv}}(x)$ from Source ($x=0, V=0$) to Drain ($x=L, V=V_{DS}$) yields the classical quadratic current equations:

• Linear Regime ($V_{DS} < V_{GS} - V_{th}$): $I_D = \mu_{\text{eff}} C_{ox} \frac{W}{L} \left[(V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right]$.
• Pinch-Off Saturation ($V_{DS} \ge V_{GS} - V_{th}$): Inversion charge drops to zero at the drain edge ($Q_{\text{inv}}(L) = 0$), clamping saturation current at $I_{D,\text{sat}} = \frac{1}{2} \mu_{\text{eff}} C_{ox} \frac{W}{L} (V_{GS} - V_{th})^2$.

High-Field Transport & Carrier Velocity Saturation ($v_{\text{sat}}$)

In sub-micron transistors ($L < 100\text{ nm}$), lateral electric fields routinely exceed $50\text{ kV/cm}$. At these extreme fields, electrons scatter violently by emitting optical phonons ($E_{\text{phonon}} \approx 63\text{ meV}$ in silicon), capping carrier drift velocity at the fundamental physical limit $v_{\text{sat}} \approx 1.0 \times 10^7\text{ cm/s}$.

Because velocity saturates before geometric pinch-off occurs, the drain saturation voltage collapses to $V_{D,\text{sat}} = \mathcal{E}_{\text{crit}} L \parallel (V_{GS} - V_{th})$. Consequently, short-channel current scales linearly with gate overdrive rather than quadratic:

• Critical Field: $\mathcal{E}_{\text{crit}} = \frac{2 v_{\text{sat}}}{\mu_{\text{eff}}} \approx 20\text{ to } 40\text{ kV/cm}$.
• Linear $I_D$ Scaling: $I_{D,\text{sat}} \approx W C_{ox} v_{\text{sat}} (V_{GS} - V_{th} - V_{D,\text{sat}})$.

Low-Field Mobility Degradation ($\mu_{\text{eff}}$) & Scattering Mechanisms

Silicon in bulk possesses an electron mobility $\mu_n \approx 1400\text{ cm}^2/\text{V}\cdot\text{s}$. However, inside an inverted MOSFET channel, electrons are squeezed against the gate oxide by intense transverse electric fields ($\mathcal{E}_{\text{eff}} > 1\text{ MV/cm}$), dragging mobility down to $200–350\text{ cm}^2/\text{V}\cdot\text{s}$.

According to Matthiessen's Rule, total carrier mobility is limited by three independent quantum scattering mechanisms acting in parallel:

• Phonon Scattering ($\mu_{\text{ph}} \propto T^{-3/2} \mathcal{E}_{\text{eff}}^{-1/3}$): Thermal lattice vibrations scattering carriers.
• Coulomb Scattering ($\mu_{\text{coul}} \propto T^{3/2} / N_{\text{ion}}$): Deflection by ionized dopant and oxide interface charges.
• Surface Roughness Scattering ($\mu_{\text{sr}} \propto \mathcal{E}_{\text{eff}}^{-2}$): Quantum reflections from atomic-scale step terraces ($R_a \sim 0.2\text{ nm}$).

Drain-Induced Barrier Lowering (DIBL) & $V_{th}$ Roll-Off

In a long-channel MOSFET, the potential barrier separating the source from the channel is controlled solely by the gate voltage. But as channel length $L_g$ scales below $30\text{ nm}$, the drain depletion region extends deep into the channel. High drain bias ($V_{DS} = V_{DD}$) reaches across and physically pulls down the source injection barrier!

This phenomenon, Drain-Induced Barrier Lowering (DIBL), manifests as a severe drop in threshold voltage with drain voltage, accompanied by exponential increase in off-state leakage:

• DIBL Metric: $\text{DIBL} = -\frac{V_{th}(V_{DD}) - V_{th}(V_{DS,\text{lin}})}{V_{DD} - V_{DS,\text{lin}}} \text{ (Target: } < 50\text{ mV/V)}$.
• Electrostatic Screening Length: $\lambda = \sqrt{\frac{\epsilon_{\text{ch}}}{2\epsilon_{ox}} t_{\text{ch}} t_{ox}}$. To suppress DIBL, foundries require $L_g > 4.5 \lambda$.

Subthreshold Swing ($S$) & The 60 mV/decade Thermal Limit

When $V_{GS} < V_{th}$, a transistor is not abruptly zero current. Instead of drift, current flows via diffusion of high-energy carriers overcoming the source barrier. The drain current drops exponentially with gate voltage according to Boltzmann statistics:

The Subthreshold Swing ($S$) measures the gate voltage change needed to reduce off-state current by one order of magnitude ($10\times$). It is determined by the capacitive voltage divider between the oxide capacitance $C_{ox}$ and depletion capacitance $C_{\text{dep}}$:

• Body Factor: $m = 1 + \frac{C_{\text{dep}}}{C_{ox}} = 1 + \frac{\epsilon_s / W_{\text{dep}}}{\epsilon_{ox} / t_{ox}}$.
• Fundamental Limit: At $T = 300\text{ K}$, $\frac{k_B T}{q} \ln(10) \approx 59.6\text{ mV/decade}$. No standard FET can switch faster than this thermal wall!

Gate-Induced Drain Leakage (GIDL) & Band-to-Band Tunneling (BTBT)

Even if subthreshold swing and DIBL are well-behaved, a third leakage mechanism strikes at high drain bias when the gate is turned hard off ($V_{GS} = 0, V_{DS} = V_{DD}$): Gate-Induced Drain Leakage (GIDL).

The large negative voltage across the gate-to-drain overlap region ($V_{GD} = -V_{DD}$) creates an immense vertical electric field exceeding $10\text{ MV/cm}$ in the heavily doped $n^+$ drain extension. This field bends the silicon energy bands so steeply that electrons in the valence band quantum-tunnel directly into the conduction band (Band-to-Band Tunneling, BTBT), causing parasitic leakage into the substrate.

• Exponential BTBT: $J_{\text{BTBT}} = A \mathcal{E}^2 \exp(-B / \mathcal{E})$, where $B \approx 21.3\text{ MV/cm}$ for silicon.
• Mitigation: Lightly Doped Drains (LDD) and dielectric gate-drain spacer engineering.

2D/1D Quantum Subband Splitting in Ultra-Thin Bodies (UTB) & Nanosheets

When the silicon body thickness $T_{\text{body}}$ in FinFETs or nanosheets shrinks below $5\text{ nm}$, the channel thickness becomes comparable to the de Broglie wavelength of conduction electrons ($\lambda_{dB} \approx 3\text{ nm}$). Carriers can no longer be treated as a 3D continuum gas; quantum mechanical confinement splits the conduction band into discrete 2D subbands:

Solving the 1D Schrödinger equation in an infinite quantum well yields quantized ground-state energies:

• Ground State Energy: $E_n = \frac{\hbar^2}{2 m_z^*} \left(\frac{n \pi}{T_{\text{body}}}\right)^2$.
• Valley Splitting in Si $\{100\}$: The 6 conduction band valleys split into 2 unprimed valleys with heavy longitudinal mass ($m_l = 0.98 m_0$) in the confinement direction and 4 primed valleys with light transverse mass ($m_t = 0.19 m_0$). The lower subband provides higher in-plane transport mobility!

Landauer-Büttiker Ballistic Transport & Quantum Conductance

When the channel length $L_g$ drops below the carrier mean free path ($L_g < \lambda_{\text{mfp}} \approx 10–15\text{ nm}$ in silicon), electrons traverse from source to drain without undergoing a single scattering event. Classical drift-diffusion mobility becomes irrelevant; current is governed by the Landauer-Büttiker Ballistic Transport formalism:

Current is limited not by channel friction, but by the finite number of transverse quantum modes $M$ that can fit across the channel width and the fundamental quantum of conductance $G_0 = 2q^2 / h$:

• Conductance Quantum: $G_0 = \frac{2q^2}{h} \approx 77.48\,\mu\text{S} \implies R_{\text{contact,min}} = \frac{h}{2q^2 M} \approx \frac{12.9\,\text{k}\Omega}{M}$.
• Ballistic Ratio ($\mathcal{B}$): $\mathcal{B} = \frac{\lambda_{\text{mfp}}}{\lambda_{\text{mfp}} + L_g}$. For $12\text{ nm}$ GAA nanosheets, $\mathcal{B} \approx 0.70–0.85$.

Coupled Poisson-Schrödinger & Non-Equilibrium Green's Function (NEGF)

To accurately simulate 2nm GAA nanosheets and CFETs, commercial TCAD tools solve the coupled Poisson-Schrödinger equations self-consistently using the Non-Equilibrium Green's Function (NEGF) method on open boundary systems:

The device Hamiltonian matrix $H$ is augmented by open contact self-energy matrices $\Sigma_S(E)$ and $\Sigma_D(E)$ that account for electron injection and absorption by the semi-infinite source/drain reservoirs:

• Retarded Green's Function: $G(E) = \left[ (E + i\eta)I - H - \Sigma_S(E) - \Sigma_D(E) \right]^{-1}$.
• Broadening Function: $\Gamma_{S,D} = i \left[ \Sigma_{S,D} - \Sigma_{S,D}^\dagger \right]$, representing carrier injection lifetime.
• Density Matrix: $\rho = \frac{1}{2\pi} \int \left[ G \Gamma_S G^\dagger f_S(E) + G \Gamma_D G^\dagger f_D(E) \right] dE$.

Industry-Standard Compact Models: BSIM-CMG, BSIM-BULK & PSP

Commercial foundries (TSMC, Samsung, Intel) cannot deliver TCAD numerical solvers to circuit designers because simulating 50 billion transistors with finite-element PDE solvers would take 1,000 years per clock cycle. Instead, device physicists develop Compact SPICE Models:

The internationally standardized compact model for FinFET and GAA nanosheet architectures is BSIM-CMG (Compact Multi-Gate), developed at UC Berkeley. BSIM-CMG utilizes a core surface-potential formulation solved analytically from Poisson's equation, guaranteeing zero mathematical singularities in charge, transconductance ($g_m$), and transcapacitance ($C_{ij}$) matrices across all operating corners.

• Continuous Across Regimes: Smooth unified transitions from subthreshold diffusion to strong-inversion velocity saturation.
• Symmetric Linearization: Preserves Gummel symmetry ($I_D(-V_{DS}) = -I_D(V_{DS})$) crucial for RF distortion analysis.

TCAD Process Calibration to Fab Silicon & Parasitic $R_{SD}$

In technology nodes below $5\text{ nm}$, the intrinsic transistor channel has become so short ($L_g \approx 12\text{ nm}$) that channel resistance is no longer the primary speed limiter. The true killer of modern PPA is Parasitic Source/Drain Resistance ($R_{SD}$):

Total device resistance is $R_{\text{total}} = R_{\text{channel}} + 2 R_{SD}$, where $R_{SD} = R_{\text{contact}} + R_{\text{sheet}} + R_{\text{spreading}}$. As nanosheet contact contact areas shrink into atomic-scale slots, contact resistance skyrockets unless contact resistivity $\rho_c$ drops below $1.0 \times 10^{-9}\,\Omega\cdot\text{cm}^2$ using advanced silicide/germanide alloys (e.g. TiSi, NiPtSi):

• Current Degradation: Extrinsic transconductance degrades: $g_{m,\text{ext}} = \frac{g_{m0}}{1 + g_{m0} R_S}$.
• Foundry PDK Rule: If $R_{SD} > 15\,\% R_{\text{total}}$, node speedup benefits are almost completely erased!

10-Year Device Reliability Physics: BTI Threshold Creep, HCD & TDDB

Foundries qualify microchips for 10-year operating lifetimes ($100{,}000\text{ hours}$) under rigorous automotive and hyperscale temperature corners ($-40^\circ\text{C}$ to $+125^\circ\text{C}$). Over lifetime, three microscopic degradation physics dominate device mortality:

• Bias Temperature Instability (BTI): Negative BTI in pFETs and Positive BTI in nFETs depassivate Si-H bonds at the gate interface, trapping positive/negative charges that shift threshold voltage: $\Delta V_{th}(t) = A \cdot t^n V_{GS}^\gamma \exp(-E_a / k_B T)$ with $n \approx 0.16–0.25$.
• Hot Carrier Degradation (HCD): Energetic electrons accelerated by lateral pinch-off fields smash into the dielectric spacer, generating interface trap states.
• Time-Dependent Dielectric Breakdown (TDDB): High gate electric fields generate percolating oxygen vacancy chains through $\text{HfO}_2$, leading to catastrophic dielectric short-circuit.