What is Etching?
After the photoresist has been developed, our circuit pattern is like a stencil lying on top of the silicon wafer. But the circuit isn't carved into the chip yet!
Etching is the process of carving away the exposed material. The hardened photoresist acts like a protective umbrella, shielding the parts we want to keep while reactive chemicals eat away the unprotected valleys.
- Etching: Carving permanent geometric trenches and holes into underlying silicon or metal.
- Masking Shield: Photoresist or hardmask layers blocking the chemical attack.
Wet Acid Baths vs Glowing Dry Plasma
In early chipmaking, wafers were dipped in tubs of warm acid (wet etching). But liquids slosh sideways underneath the mask, eating away walls like water hollowing out a riverbank!
Modern fabs use dry plasma etching. Inside a metal vacuum chamber, high-frequency electricity ignites gas into a glowing purple plasma, shooting energetic ions straight down like millions of microscopic darts!
- Wet Etch: Liquid chemicals eating in all directions (isotropic).
- Dry Plasma Etch: Energetic gas ions shooting straight down (anisotropic).
Straight Down: Anisotropy
Imagine digging a hole in dry beach sand: the walls crumble and cave in. But computer chips need walls that stand 100% straight and vertical, like the walls of a skyscraper.
Dry etching combines chemical etching (gases that eat atoms) with physical ion bombardment (heavy ions hammering straight down). This unique combo carves perfectly vertical canyons without eating sideways!
- Anisotropy ($A$): Carving purely downward without lateral undercut ($A = 1.0$).
- Undercut: Unwanted sideways erosion underneath the protective mask edges.
Level 1 Completed: Carving Microscopic Canyons Mastery Certificate
Conferred for mastery of Level 1 (Academic Level 1 • Ages 6–10) curriculum, simulation laboratory, and assessment evaluation.
Generating the RF Plasma Sheath
How do you create a plasma inside an etch chamber? We pump the chamber down to a few millitorr of pressure and introduce process gases like carbon tetrafluoride ($CF_4$) and argon ($Ar$).
We apply 13.56 MHz Radio Frequency (RF) voltage between two metal plates. Because light electrons oscillate much faster than heavy positive ions, the wafer electrode self-charges to a strong negative DC bias voltage. This creates an electric 'sheath' that accelerates positive ions like bullets straight into the wafer!
- 13.56 MHz RF Generator: Industrial standard frequency for igniting and sustaining glow discharges.
- DC Self-Bias Voltage ($V_{dc}$): Negative potential accelerating ions across the plasma sheath.
The Etch Chemistry Toolkit (CF4, SF6, Cl2, HBr)
Different materials require different plasma gases. To etch silicon dioxide ($SiO_2$) glass, we use fluorocarbon gases ($CF_4, C_4F_8$) because fluorine atoms react with silicon to form volatile silicon tetrafluoride ($SiF_4\uparrow$) gas.
To etch pure crystalline silicon or polysilicon gates with ultra-high selectivity over thin gate oxides, we switch to chlorine ($Cl_2$) and hydrogen bromide ($HBr$). Bromine reacts vigorously with silicon but will not attack silicon dioxide, delivering selectivity ratios exceeding 100:1!
- Fluorine Chemistries ($CF_4, SF_6$): Fast etch for $SiO_2$ and $Si_3N_4$ producing volatile $SiF_4\uparrow$.
- Bromine/Chlorine Chemistries ($HBr, Cl_2$): Ultra-high selectivity silicon gate etch forming $SiBr_4\uparrow$.
Sidewall Passivation: The Fluorocarbon Secret
Why doesn't the reactive fluorine gas eat sideways into the trench walls? The secret is simultaneous deposition and etching!
As $CF_4$ or $CHF_3$ gas dissociates, it deposits an ultra-thin Teflon-like fluorocarbon polymer ($CF_x$) everywhere. On the bottom of the trench, energetic ions bombard and destroy this polymer instantly. But on the vertical sidewalls, no ions strike—the protective polymer stays intact, blocking chemical attack completely!
- In-Situ Passivation: Teflon-like fluorocarbon film ($CF_x$) coating sidewalls.
- Ion-Assisted Clearing: Directional ion bombardment clearing polymer exclusively from horizontal floors.
Level 2 Completed: RF Plasmas & Fluorocarbon Chemistries Mastery Certificate
Conferred for mastery of Level 2 (Academic Level 2 • Ages 11–13) curriculum, simulation laboratory, and assessment evaluation.
Decoupling Density & Bias: The ICP Breakthrough
In legacy capacitively coupled Reactive Ion Etching (RIE), a single RF power supply controlled both plasma density (number of ions) and bias voltage (speed of ions). You could not increase the etch rate without blasting the wafer with destructive high-energy ions.
Inductively Coupled Plasma (ICP) revolutionized dry etching by using two independent power supplies: (1) a top inductive coil (ICP source power) generates ultra-dense plasma ($10^{11} - 10^{12}\, ext{cm}^{-3}$), while (2) a bottom capacitive electrode (RF bias power) independently tunes ion acceleration energy.
- ICP Source Power: Controls radical and ion generation density independently.
- RF Bias Power: Controls vertical ion bombardment kinetic energy and directional momentum.
Ion-Enhanced Chemical Etching (Coburn & Winters)
In 1979, John Coburn and Harold Winters conducted a landmark experiment proving that dry plasma etching is not purely physical or purely chemical, but a synergistic combination called 'Ion-Enhanced Chemical Etching'.
Exposing silicon to xenon difluoride ($XeF_2$) gas alone produced a sluggish etch rate (5 Å/min). Firing argon ions ($Ar^+$) alone produced slow physical sputtering (2 Å/min). But combining $XeF_2$ gas and $Ar^+$ ions simultaneously exploded the etch rate to over 55 Å/min—an order of magnitude higher than the sum of both individual rates!
- Synergy Factor: $R_{ ext{combo}} \gg R_{ ext{chemical}} + R_{ ext{physical}}$.
- Damage-Promoted Reaction: Ion impact shatters surface silicon bonds, allowing halogen radicals to react instantaneously.
Profile Anomalies: Bowing, Notching & Micro-Trenching
Controlling vertical sidewall profiles requires avoiding three classical plasma defects: (1) 'Bowing'—sidewalls curving convex like an archery bow due to scattered ions eroding passivating polymers midway down the trench.
(2) 'Micro-trenching'—ions grazing off tapered sidewalls like billiard balls, focusing extra ion flux at the base corners and digging sharp grooves, and (3) 'Notching'—electrical charging of dielectric bottoms deflecting low-energy ions laterally, gouging re-entrant notches into conductive polysilicon gates.
- Bowing Defect: Lateral sidewall bulging caused by scattered energetic ions.
- Notching Defect: Lateral re-entrant cut at conductor-dielectric interfaces caused by local electrostatic charging.
Level 3 Completed: ICP-RIE Physics & Profile Engineering Mastery Certificate
Conferred for mastery of Level 3 (Academic Level 3 • Ages 14–18) curriculum, simulation laboratory, and assessment evaluation.
Aspect Ratio Dependent Etching (ARDE / RIE Lag)
In an ideal world, all holes on a wafer would etch at the exact same speed regardless of size. In reality, narrow contact holes etch significantly slower than wide trenches—a phenomenon known as Aspect Ratio Dependent Etching (ARDE) or RIE Lag.
As a hole deepens and its aspect ratio ($AR = ext{Depth} / ext{Diameter}$) climbs past $10:1$, gas molecules inside the hole transition into the Knudsen diffusion regime. Reactant radicals bounce against sidewalls thousands of times before reaching the bottom, starving the etch front.
- RIE Lag: The progressive deceleration of etch rate as feature aspect ratio increases.
- Knudsen Diffusion Regime: Mean free path exceeds hole diameter ($\lambda_{ ext{mfp}} \gg d_{ ext{feature}}$).
Microloading & Macroloading Dynamics
Loading effects occur when local chemical reactant consumption depletes the supply of etchant radicals. Macroloading refers to the global wafer effect: a wafer with 80% exposed silicon area consumes radicals far faster than a wafer with only 5% exposed area, dropping etch rate globally.
Microloading occurs locally across single chips: an isolated gate line surrounded by large open fields receives a massive flux of laterally diffusing radicals, etching significantly faster than dense gate arrays at tight pitch. Advanced etch recipes utilize high gas residence flows ($> 500\, ext{sccm}$) and low pressures to suppress loading.
- Macroloading: Wafer-scale etch rate drop proportional to total exposed pattern area.
- Microloading: Pitch-dependent etch rate disparity between isolated and dense features.
Ion Shadowing & Neutral Starvation
In deep narrow contact holes, ions entering at slight off-normal angles (thermal angular spread $ heta_{ ext{div}} \sim 2^\circ-5^\circ$) collide with top sidewall corners rather than reaching the bottom floor.
This 'ion shadowing' starves the hole base of activating kinetic energy. Concurrently, reaction byproducts ($SiF_4\uparrow$) attempting to escape out the top collide with incoming etchant radicals, choking mass transport. Overcoming this bottleneck requires pulsed RF bias to allow periodic byproduct clearance.
- Ion Shadowing Angle: $ heta_{ ext{crit}} = rctan(d / h)$ (defining the optical acceptance cone for ions).
- Byproduct Choking: High Knudsen resistance trapping reaction byproducts inside deep holes.
Level 4 Completed: Aspect Ratio Dependent Etching (ARDE) & Loading Mastery Certificate
Conferred for mastery of Level 4 (Academic Level 4 • Undergraduate (Freshman–Sophomore)) curriculum, simulation laboratory, and assessment evaluation.
Cryogenic Dry Etching ($-100^\circ ext{C}$ to $-20^\circ ext{C}$)
Traditional fluorocarbon sidewall passivation leaves thick polymer crusts that are difficult to clean and induce wafer stress. Cryogenic Etching cools the electrostatic wafer chuck down to $-100^\circ ext{C}$ using liquid nitrogen chillers.
At cryogenic temperatures, purely chemical spontaneous etching of silicon by fluorine atoms drops to absolute zero because the thermal reaction barrier ($E_a$) cannot be overcome. Vertical sidewalls remain completely frozen and immune to attack without requiring any polymer passivating gas!
- Cryogenic Cooling: Liquid nitrogen chilled chuck ($T_{\text{wafer}} \le -80^\circ\text{C}$).
- Zero Polymer Clean: Pure $SF_6 / O_2$ chemistry leaving pristine atomic sidewalls without carbon residue.
Optical Emission Spectroscopy (OES) Endpointing
Etching an ultra-thin 2.0 nm gate or contact layer cannot rely on timed recipes; etching for just 2 seconds too long would punch through the underlying interface. Etch chambers monitor Optical Emission Spectroscopy (OES) in real time.
As plasma electrons collide with volatile etch byproducts, atoms emit light at characteristic quantum wavelengths (e.g. $SiF$ emits at 440 nm; $CN$ emits at 387 nm). When the underlying layer is reached, byproduct emission collapses instantly, triggering automated RF plasma termination within 50 milliseconds.
- OES Spectrometer: Fiber-optic spectrometer monitoring multi-channel optical emission spectra.
- Endpoint Detection: Automated derivative algorithms ($ rac{dI}{dt} = ext{inflection}$) halting plasma at interface.
Interferometric Endpoint & In-Situ Thickness Control
For transparent dielectric films ($SiO_2, Si_3N_4$), endpoint systems shine a dedicated laser diode (670 nm) or broad xenon lamp directly through a quartz window onto the wafer during etching.
Light reflecting from the top etching surface interferes with light reflecting from the bottom buried interface. As the film thins, the reflected intensity oscillates cyclically in sinusoidal interference fringes. Counting fringe peaks reveals real-time film thickness down to $\pm 0.5\, ext{nm}$.
- Interferometric Endpoint: Measuring optical interference fringes in real time.
- Fringe Period Equation: Each sinusoidal fringe period corresponds to $\Delta d = \lambda / (2n)$ film removed.
Level 5 Completed: Cryogenic Etch & Optical Emission Spectroscopy (OES) Mastery Certificate
Conferred for mastery of Level 5 (Academic Level 5 • Advanced Undergraduate (Junior–Senior)) curriculum, simulation laboratory, and assessment evaluation.
The Self-Limiting ALE Cycle
When transistor dimensions approached single nanometers, conventional plasma etching suffered from severe micro-roughness and damage. Atomic Layer Etching (ALE) is the precise reverse of ALD: a cyclic, self-limiting process removing exactly one atomic monolayer at a time.
A standard silicon ALE cycle consists of four distinct steps: (1) Chlorine ($Cl_2$) dosing forms a self-terminating chemisorbed $SiCl_x$ monolayer. (2) Inert gas purge evacuates unreacted gas. (3) Low-energy Argon ion ($Ar^+$) bombardment selectively desorbs only the chlorinated silicon atoms without touching underlying pristine silicon. (4) Final purge resets the chamber.
- Surface Chlorination Half-Cycle: Self-limiting chemisorption saturated at 1 monolayer.
- Sub-Threshold Ion Sputtering: Argon ion energy kept between desorption threshold and physical sputter threshold ($E_{\text{desorb}} < E_{\text{ion}} < E_{\text{sputter}}$).
The ALE Energy Window ($E_{\text{threshold}}$ vs $E_{\text{sputter}}$)
The operational foundation of directional ALE is the 'ALE Energy Window'. The ion bombardment energy must be tuned with extreme precision.
If ion energy ($E_{\text{ion}}$) is below the desorption threshold ($E_{\text{desorb}} \approx 20\, ext{eV}$), the chlorinated $SiCl_x$ atoms cannot be dislodged (zero etching). If ion energy exceeds the physical sputtering threshold ($E_{\text{sputter}} \approx 45\, ext{eV}$), ions knock out unreacted silicon atoms non-selectively, losing self-limiting control. Operating inside this narrow $25\,\text{eV}$ window guarantees atomic perfection.
- Desorption Threshold ($E_{\text{desorb}}$): Minimum energy to desorb chemisorbed reaction products ($\sim 20\, ext{eV}$).
- Physical Sputter Threshold ($E_{\text{sputter}}$): Energy where pristine, unreacted material begins sputtering physically ($\sim 45\, ext{eV}$).
Thermal ALE & Ligand Exchange for Dielectrics
Directional plasma ALE works brilliantly for silicon, but gate dielectrics ($Al_2O_3, HfO_2$) in 3D Gate-All-Around (GAA) nanosheets require isotropic, damage-free removal on vertical and horizontal faces simultaneously.
Thermal ALE achieves isotropic atomic removal using sequential vapor reactions without ions! Half-cycle 1 fluorinates the metal oxide surface using hydrogen fluoride ($HF$), forming a metal fluoride skin. Half-cycle 2 exposes the surface to organometallic precursors (e.g. $Sn(acac)_2, Al(CH_3)_3$), triggering ligand exchange that converts the metal fluoride into volatile complexes.
- Fluorination / Ligand Exchange: Converting non-volatile oxides into volatile metal coordination complexes.
- 3D Isotropic ALE: Flawless $100\%$ conformal atomic trimming inside nanosheet cavities.
Level 6 Completed: Atomic Layer Etching (ALE) Kinetics Mastery Certificate
Conferred for mastery of Level 6 (Academic Level 6 • Master of Science (M.S.) & Graduate) curriculum, simulation laboratory, and assessment evaluation.
3D NAND High-Aspect-Ratio (HAR > 100:1) Channel Drilling
In 3D NAND flash memory, chips stack over 300 vertical wordline layers consisting of alternating oxide and nitride ($SiO_2 / Si_3N_4$, ONON) or oxide and polysilicon (OP) films. Fabricating memory cells requires drilling billions of vertical channel holes through this 10-micrometer thick sandwich.
Channel holes have a top diameter of 80 nm and penetrate 10,000 nm deep—an extreme aspect ratio ($AR > 100:1$). At this depth, maintaining verticality requires multi-frequency RF bias generators (2 MHz + 60 MHz), high-energy ions ($> 3\,\text{keV}$), and heavy carbon hardmasks (amorphous carbon, ACL) with exceptional sputtering resistance.
- Extreme Aspect Ratio ($AR > 100:1$): Drilling 10µm deep vertical holes through 300+ material pairs.
- Multi-Frequency Bias (2 MHz / 60 MHz): Low-frequency bias driving high-energy collimated ions to the hole floor.
Sacrificial SiGe Nanosheet Cavity Release (>150:1 Selectivity)
In Gate-All-Around (GAA) nanosheets and 3D Complementary FETs (CFET), alternating crystalline sheets of silicon ($Si$) and silicon-germanium ($Si_{0.7}Ge_{0.3}$) are grown epitaxially. To wrap the gate around all four sides of each nanosheet, the sacrificial $SiGe$ sheets must be completely removed.
The etch chemistry—typically vapor-phase acetic acid / hydrogen peroxide / hydrofluoric acid ($CH_3COOH / H_2O_2 / HF$) or thermal downstream plasma ($CF_4 / O_2 / N_2$)—must achieve a selectivity exceeding 150:1 over pure silicon. Any etching of the silicon nanosheet causes sheet thinning, surface roughness, and catastrophic threshold voltage variation.
- Cavity Release Selectivity: $S = rac{R_{ ext{SiGe}}}{R_{ ext{Si}}} > 150:1$ (preserving 3nm active silicon channel sheets).
- Capillary Release Stiction: Vapor-phase etching completely preventing nanosheet pull-in stiction.
Chamber Wall Surface Dynamics & Plasma Drift
Over thousands of processed wafers, chamber walls accumulate fluorocarbon polymer deposits and metallic flakes. Wall surface conditions alter the heterogeneous recombination rate of etchant radicals (e.g. $F + F \xrightarrow{\text{wall}} F_2$), causing radical concentration drift and run-to-run CD shifts.
High-volume fabs implement Waferless Auto-Clean (WAC) cycles: between every wafer (or lot), an oxygen/plasma clean vaporizes polymer buildup, followed by a seasoning pulse that coats the chamber walls with a standardized nanometer conditioning film, locking in run-to-run repeatability.
- Waferless Auto-Clean (WAC): Automated oxygen plasma stripping chamber wall deposits between wafers.
- Wall Conditioning: Enforcing constant radical wall recombination coefficients ($\gamma_{ ext{wall}}$).
Level 7 Completed: Frontier 3D NAND Drilling & GAA Nanosheet Release Mastery Certificate
Conferred for mastery of Level 7 (Academic Level 7 • Ph.D., Research Scientist & Technical Fellow) curriculum, simulation laboratory, and assessment evaluation.