3D NAND Peripheral Gate Etch
Peripheral gate etch cuts the HV and LV poly gates that make the periphery's two different transistor types work, and it has to do it as a single pass over a surface that is already two different gate-oxide thicknesses by the time this etch runs.
That dual thickness is not this etch's problem to create — it just has to respect it.
High-voltage and low-voltage transistors need different gate oxide thicknesses for a simple reason. HV transistors, used for charge pumps and word-line drivers that switch tens of volts, need a thicker gate oxide to survive that voltage without breaking down; LV transistors doing ordinary logic switching get a thinner oxide that switches faster at lower voltage. Both thicknesses exist on the same wafer, side by side, before poly gate etch ever runs.
Poly gate etch is one mask, one etch chemistry, applied across both regions at once. A blanket poly layer deposited over the whole dual-oxide surface gets patterned and etched down to the gate shapes for both HV and LV transistors simultaneously — the etch itself doesn't distinguish between the two oxide thicknesses it's landing on, which is exactly what makes stopping cleanly on either one, without punching through the thinner LV oxide nearby, the real challenge.
Overetch risk is asymmetric between the two regions. Because LV gate oxide is thinner, any etch chemistry aggressive enough to reliably clear poly everywhere risks punching through the thin LV oxide into the silicon channel underneath, damaging a transistor that otherwise had nothing wrong with its own gate etch — the HV side has more margin simply because its oxide started thicker.
This etch inherits the hard problem from the step before it, not from itself. The dual-oxide patterning that created two different thicknesses in the first place — growing or depositing thick oxide, then selectively thinning it in the LV regions — did the harder lithography and film work; gate etch's job is simply not to undo that careful thickness control by overetching into the thinner side.
Gate spacer etch follows immediately after, on every gate this step just cut. That next step defines the source/drain extension boundary for both HV and LV transistors, building directly on whatever gate profile this etch leaves behind — any gate-etch irregularity here becomes a spacer-etch problem one step later.
Peripheral gate etch is where dual-voltage logic design meets ordinary poly-gate patterning: Samsung's V-NAND, SK hynix's 4D NAND, Kioxia/WD's BiCS, Micron, and YMTC's Xtacking all cut HV and LV gates with this same single etch pass, and the real engineering challenge was already solved one step earlier, at HV GOX patterning — this etch's job is simply to not waste that work.