Bicmos Logic 1980s Propose Merging Bipolar and CMOS on One Die

# BiCMOS Logic (Late 1980s): Step 3 — Propose Merging Bipolar and CMOS on One Die

## 1. Why Not Just Pick the Right Tool for Each Job

Steps 1 and 2 establish a clean complementarity: CMOS is dense and nearly free to leave idle, but weak at driving large loads; bipolar drives large loads well, but is neither dense nor free to leave idle. Neither fact is new by the late 1980s — what changes is the willingness to pay a single process-integration cost once, up front, in exchange for being able to place either device type wherever a given circuit needs it. This is the premise this entire series calls BiCMOS: not a replacement for CMOS or bipolar, but a merged process that builds a bipolar transistor and a CMOS transistor pair on the same die, so a designer can use CMOS gates for the bulk of a design's logic and bipolar output stages only at the specific nodes — large buses, output pads, heavily loaded internal nets — where bipolar's drive strength earns its area and power cost back.

## 2. What a Merged Process Actually Has to Do

A BiCMOS process flow has to produce, side by side on the same wafer, the n-well and p-well structures a CMOS pair needs and the buried collector, base, and emitter diffusions a bipolar transistor needs — without either device's processing steps degrading the other's. That is a nontrivial integration problem, not a simple combination of two existing flows run back to back, and it is the subject of the next two steps. The payoff this step stakes out is specific: a BiCMOS chip can hold its static power close to a pure-CMOS chip's near-zero floor for the overwhelming majority of its gates, while reserving bipolar's drive strength for the minority of nodes where pure CMOS output drive would otherwise set the chip's speed ceiling.

## 3. Companion Diagram One: Quantitative View

Two Devices, Two Different Jobs on One Die fraction of gates vs role in a representative BiCMOS design CMOS gates — bulk logic, dense, idle-cheap bipolar stages — selected output/driver nodes only the split a BiCMOS floorplan actually uses most of the gate count, most of the die area a small fraction of nodes, chosen deliberately BiCMOS is an allocation strategy, not a universal substitution CMOS everywhere it is good enough; bipolar only where it has to be

## 4. Companion Diagram Two: Structural View

One Die, Two Transistor Families, One Process Flow what a merged BiCMOS wafer must carry simultaneously CMOS REGION n-well / p-well pair, planar MOSFETs SHARED SUBSTRATE common wafer, common thermal budget BIPOLAR REGION buried collector, base, emitter diffusions the integration challenge: build both without either degrading the other

Take bicmos logic 1980s propose merging bipolar and cmos on one die further

Ask the copilot about this term, or have our engineers assess it against your process.

Ask CFSGPT about this → Request a technical assessment → Open the CFS app