Bipolar Ecl 1960s Exploit the Wired or Capability
# Bipolar ECL Logic (1960s): Step 8 — Exploiting the Wired-OR Capability
A logic function ECL gets almost for free, that saturating logic families cannot offer safely. Step 4 noted that multiple emitter-follower outputs can be tied to a single node without damage, because whichever follower's input is highest simply wins the node and the others stop conducting. This step works out why that is true, what logic function it implements, and why attempting the same trick in TTL or DTL would risk damaging the gates.
## 1. Why Tying ECL Outputs Together Is Safe
An ECL output stage's emitter follower has no pull-down path of its own in the simplest configuration — it only actively pulls its output up toward its own collector-switch level, and relies on a shared pull-down (either a resistor to the negative rail or another biasing scheme) to bring the node down when no follower is driving it high. When several such outputs are tied together, whichever gate currently has the higher internal collector voltage pulls the shared node to its own high level, and the follower transistors on the other tied outputs simply see their base below their emitter and stop conducting — they are driven into cutoff, not into a damaging short-circuit condition, because non-conducting is their default safe state. In a totem-pole TTL output, by contrast, tying two outputs together can place one gate's low-impedance pull-up directly against another gate's low-impedance pull-down, drawing a large fault current that can destroy both outputs — which is why wired-OR was never offered as a supported TTL feature.
## 2. Real Diagram: Wired-OR Node From Multiple Emitter Followers
## 3. What Wired-OR Buys a 1960s Logic Designer
Because the shared node goes to the high (logic '1') level if any one of the tied gates outputs a '1', wired-OR directly implements an OR function (or, read the other way with ECL's negative logic convention, a NOR/AND relationship) without consuming an additional gate, additional propagation delay, or additional board area for a separate OR gate package. 1960s ECL designers used this heavily to build wide AND/OR logic trees, address decoders, and priority structures directly on the backplane wiring, trading a small amount of noise-margin budget (the wired node has to tolerate whichever output is actively driving it, plus the capacitive loading of every tied output) for a real reduction in gate count and interconnect delay in exactly the high-speed control logic ECL was chosen for.
## 4. Companion Diagram: Stage Sequence and Trend Summary
## Exploiting the Wired-OR Capability's Place in the Process Lineage
This is step 8 of 20 in the Bipolar ECL Logic (1960s) series, covering wired-OR as a structural consequence of the emitter-follower output stage, unique among 1960s logic families to non-saturating current-mode circuits.