CMOS Crossover 1980 Test Margin Against Hmos Ii Specifically

# Run the Harder Test: Does the Margin Survive Against NMOS's Best Possible Answer

## 1. Substitute HMOS-II's Numbers for First-Generation HMOS's

Step 6 confirmed CMOS's power advantage survives against first-generation HMOS once every guard-ring and decoupling-capacitance cost from Steps 2 through 5 is included. That is not the hardest test available. The 1978 series' own Step 8 pushed HMOS into a second generation — HMOS-II, scaled to roughly a 2.0 micron channel length and clock speeds near 10 MHz — specifically to find NMOS's physical ceiling. If CMOS's margin is to mean anything beyond a snapshot comparison, it must be tested against that ceiling, not against the generation HMOS-II had already surpassed.

$$P_{total,HMOS\text{-}II}=I_{DD}V_{dd}+C_{HMOS\text{-}II}V_{dd}^2f_{HMOS\text{-}II}$$

HMOS-II's shorter channel and thinner oxide reduce $C_{HMOS\text{-}II}$ relative to first-generation HMOS, and its higher clock speed raises $f_{HMOS\text{-}II}$ — both changes that first-generation HMOS's own Step 1 (of the 1978 series) would recognize as the expected result of further constant-voltage scaling. What HMOS-II's own numbers do not change, because Step 1 of this series already established it as structural rather than process-dependent, is $I_{DD}$: the static current a ratioed depletion-load inverter draws is set by the inverter's topology and sizing, not by how short its channel has become.

HMOS-II Shrinks the Dynamic Term, Not the Static One scaling improves C and f; I_DD stays set by the ratioed inverter's own topology HMOS (GEN 1) C_HMOS · V_dd² · f_HMOS I_DD · V_dd (static, structural) roughly 2 μm, ~10 MHz class HMOS-II (NMOS'S CEILING) C·V_dd²·f — shrunk, but term structure unchanged I_DD · V_dd — SAME TOPOLOGY, UNCHANGED 1978's Step 8: NMOS's physical limit SCALING NEVER TOUCHED THE TERM THAT DECIDED THE CROSSOVER Step 1 of the 1978 series already proved this: I_DD is circuit topology, not channel length so the harder test reduces to one question does CMOS's shrunk dynamic term fall faster than HMOS-II's? — Section 2

## 2. Show the Margin Narrows but the Decisive Asymmetry Is Who Still Has Room to Scale

Running HMOS-II's improved $C$ and $f$ values against CMOS's own equivalently scaled dynamic term narrows the power ratio Step 6 computed — both device families benefit from the same lithography-node shrinkage, so neither side's dynamic term improves relative to the other's by much. What does not narrow is the static term: HMOS-II's $I_{DD}V_{dd}$, present at whatever scale HMOS-II's die integrates, remains exactly as structural as first-generation HMOS's was, and at HMOS-II's higher integration density the aggregate static power is, if anything, larger in absolute terms than first-generation HMOS's was at its lower density.

$$\frac{P_{total,HMOS\text{-}II}}{P_{total,CMOS,real}} > \frac{P_{total,HMOS}}{P_{total,CMOS,real}}\cdot k,\quad 0<k<1,\text{ margin narrows but does not invert}$$

The more decisive asymmetry is not found in either equation directly. It is in what the 1978 series' own Step 8 already concluded: HMOS-II was approaching NMOS's physical scaling limit — the same $E=V/L$ constraint that series' Step 1 identified had nowhere further to go without abandoning the fixed 5 V rail entirely. CMOS, carrying no equivalent static term to begin with, had no comparable ceiling forcing it to stop scaling at this density. The margin this step tests is therefore not simply numerical; it compares a technology at the end of its own documented runway against one that was, at this point in the project's lineage, still early in its own.

One Technology Hit Its Ceiling; the Other Had Not Real Diagram — the asymmetry the numbers alone do not show HMOS-II'S ROAD ENDS HERE 1978 Step 1: E = V/L has a ceiling 1978 Step 8: HMOS-II approaches it further scaling needs lower V_dd a change NMOS's topology alone can't absorb this is where this particular road stops CMOS'S ROAD CONTINUES no structural static term to begin with guard-ring/decap costs scale, don't block V_dd can fall in later generations too without reopening a term NMOS never escaped this road was still early, not late THE MARGIN NARROWS NUMERICALLY, WIDENS STRUCTURALLY today's power ratio and tomorrow's scaling headroom are two different kinds of advantage the crossover's durability rests on the second kind, not just the first this is what makes the crossover permanent rather than a temporary snapshot — Section 3

## 3. State Why This Is the Test That Settles the Crossover's Permanence

This step completes the series' verification arc in the strongest form available: not against a generic NMOS comparison, and not against the first HMOS generation this series' own Step 1 used to motivate the crossover, but against the specific endpoint the 1978 series' own lineage reached when it pushed NMOS as far as the $E=V/L$ constraint from that series' Step 1 would allow. The numerical margin narrows, exactly as expected once both families benefit from the same lithography improvements. It does not invert, and more importantly, it cannot invert through any further NMOS scaling, because the term holding it back — $I_{DD}V_{dd}$ — is not a scaling variable in the ratioed-inverter topology at all; it was never going to shrink no matter how many more HMOS generations followed HMOS-II.

This is why the crossover this series opened in Step 1 is not a snapshot comparison that a later, more refined NMOS generation could eventually reverse. CMOS's advantage rests on eliminating a structural term entirely, while HMOS-II's own best case rests on a technology that Step 1 of its own series already proved was running out of room. The series' remaining step turns from verifying the crossover to summarizing what later CMOS generations specifically inherit from the twin-well, guard-ring, and decoupling-capacitance work this series performed — separating what became permanent practice from what was particular to the 1980 generation's own process limits.

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